Abstract: Disclosed herein is an array of pixels. Each pixel includes a single photon avalanche diode (SPAD) and a transistor circuit. The transistor circuit includes a clamp transistor configured to clamp an anode voltage of the SPAD to be no more than a threshold clamped anode voltage, and a quenching element in series with the clamp transistor and configured to quench the anode voltage of the SPAD when the SPAD is struck by an incoming photon. Readout circuitry is coupled to receive the clamped anode voltage from the transistor circuit and to generate a pixel output therefrom, the threshold clamped anode voltage being below a maximum voltage rating of transistors forming the readout circuitry.

Abstract: A pixel includes a single photon avalanche diode (SPAD) having a cathode coupled to a high voltage supply through a quenching element, with the SPAD having a capacitance at its anode formed from a deep trench isolation, with the quenching element having a sufficiently high resistance such that the capacitance is not fully charged when the SPAD is struck by an incoming photon. The pixel includes a clamp transistor configured to be controlled by a voltage clamp control signal to clamp voltage at an anode of the SPAD when the SPAD is struck by an incoming photon to be no more than a threshold clamped anode voltage, and readout circuitry coupled to receive the clamped anode voltage from the clamp transistor and to generate a pixel output therefrom. The threshold clamped anode voltage is below a maximum operating voltage rating of transistors forming the readout circuitry.