Abstract: Methods and systems access an original integrated circuit (IC) design. The smallest spacing between elements in the original IC design is an “original” minimum spacing. These methods and systems automatically convert the original IC design to a reduced IC design, and the smallest spacing between elements in the reduced IC design is a “reduced” minimum spacing that is less than the original minimum spacing. Such methods and systems either automatically replace a single via in the original IC design with multiple vias in the reduced IC design (in an area where the single via was located in the original IC design) or automatically replace the single via in the original IC design with a via bar in the reduced IC design (in an area where the single via was located in the original IC design).

Abstract: Methods and systems access an original integrated circuit (IC) design. The smallest spacing between elements in the original IC design is an “original” minimum spacing. These methods and systems automatically convert the original IC design to a reduced IC design, and the smallest spacing between elements in the reduced IC design is a “reduced” minimum spacing that is less than the original minimum spacing. Such methods and systems either automatically replace a single via in the original IC design with multiple vias in the reduced IC design (in an area where the single via was located in the original IC design) or automatically replace the single via in the original IC design with a via bar in the reduced IC design (in an area where the single via was located in the original IC design).

Abstract: Methods and computer program products for decomposing and etching a circuit pattern layout are provided. The methods may include decomposing a circuit pattern layout into a first sub-pattern and second sub-pattern, where the decomposing includes: identifying, from the circuit pattern layout, a design line and a design via location associated with the design line; forming a first pattern line for the first sub-pattern corresponding to a first portion of the design line, and a second pattern line for the second sub-pattern corresponding to a second portion of the design line, with the first and second pattern lines overlapping at the design via location in an overlay of the first sub-pattern with the second sub-pattern. The first sub-pattern may be etched in a first circuit structure layer and the second sub-pattern etched in a second circuit structure layer, the etching at least partially forming a via at the design via location.