Abstract: A circuit and corresponding method generate a filtered timestamp. The circuit comprises recursive filter logic. The circuit generates the filtered timestamp from a received timestamp by filtering the received timestamp via the recursive filter logic. The recursive filter logic reduces jitter in the filtered timestamp relative to jitter of the received timestamp. The jitter represents a deviation of the received timestamp from a target (ideal) timestamp. The circuit outputs the filtered timestamp generated. The filtered timestamp is a more accurate representation of the target timestamp, relative to the received timestamp, due to the jitter reduced.

Abstract: A circuit and corresponding method perform timestamp filtering. The circuit comprises recursive filter logic that implements a recursive least-squares (RLS) filter. The circuit (i) generates a filtered timestamp from a received timestamp by filtering the received timestamp via the recursive filter logic. The recursive filter logic applies the RLS filter to a portion of the received timestamp. A number of bits of the portion is less relative to a total number of bits of the received timestamp. The circuit outputs the filtered timestamp generated. Applying the RLS filter to the portion enables the circuit to be more efficient (e.g., smaller adders, fewer flipflops, etc.), thereby reducing area and power consumption of the circuit.

Abstract: A circuit and corresponding method perform timestamp filtering. The circuit comprises input format-conversion logic that converts a received timestamp from an original format to an intermediate format. The circuit further comprises recursive filter logic coupled to the input format-conversion logic. The recursive filter logic generates a filtered timestamp in the intermediate format by filtering the received timestamp in the intermediate format. The circuit further comprises output format-conversion logic coupled to the recursive filter logic. The output format-conversion logic converts the filtered timestamp from the intermediate timestamp format to the original timestamp format and outputs the filtered timestamp in the original timestamp format. Converting the received timestamp into a different format avoids use of complex logic to handle rollover of input values, thereby reducing area and power consumption of the circuit.

Abstract: A hardware queue for an integrated circuit device includes an internal queue memory and at least one external queue memory. The internal queue memory and the external queue memory are operated as a continuous hardware queue memory by monitoring occupancy of the internal queue memory and, based on that occupancy, controlling an internal tail pointer indicating a next write point for inserting new data into the internal queue memory, an internal head pointer indicating a next read point for extracting data from the internal queue memory based on order of insertion, at least one external tail pointer indicating a next write point for inserting new data into the external queue memory, at least one external head pointer indicating a next read point for extracting data from the external queue memory based on order of insertion, and wrap pointers indicating transitions between the internal queue memory and the external queue memory.

Abstract: A FIFO memory device has a first number of data storage units and a second number of internal FIFO memories. Each internal FIFO memory has a third number of internal data storage units. The first number is a product of the second and third numbers. A fourth number of data inputs receives input data units in order. Input multiplexer circuitry connects each one of the data inputs to any one of the internal FIFO memories, for storage of input data units, in order, in a first layer of the FIFO memory device including corresponding storage locations in respective ones of the internal FIFO memories. The first layer may be physical, or may be logical and maintained by pointers. Output multiplexer circuitry coupled to the internal FIFO memories connects each of the internal FIFO memories to any one of the data outputs to read out the stored data units in order.

Abstract: An instruction execution processor has an input to receive instructions associated with maintaining a queue for storing packet identifiers (IDs) corresponding to packets being processed by a network device. A memory coupled to the instruction execution processor is for storing instructions received at the input of the instruction execution processor and not executed by the instruction execution processor. An instruction feedback processor is coupled to the instruction execution processor. The instruction feedback processor is configured to, in response to receiving an output from the instruction execution processor, identify one or more instructions, stored in the memory, that correspond to a new packet ID at the head of the queue, and feed back, to the input of the instruction execution processor, the one or more identified instructions.

Abstract: A method of performing logic synthesis of at least a part of an integrated circuit design. The method comprises identifying a first and at least one further module within the IC design that are mutually exclusive, selecting at least one register element within the first identified module and at least one register element within the at least one further identified module to be shared, and merging the first and at least one further mutually exclusive modules such that at least one common register element is shared between the first and at least one further mutually exclusive modules for the register elements selected to be shared.

Abstract: A multimode rake receiver comprise a common antenna interface, arranged to at least receive in a first mode a first CDMA radio channel carrying information encoded according to a first baseband modulation standard and to receive in a second mode a second CDMA radio channel carrying information encoded according to a second baseband modulation standard; and a common signal processing path, at least arranged to process in the first mode the first CDMA radio channel and in the second mode the second CDMA radio channel, wherein the common signal path comprises a common descrambling and de-spreading unit and a common hybrid code generating unit arranged to provide to the common descrambling and de-spreading unit chip codes applicable in the first mode to the first CDMA radio channel and in the second mode to the second CDMA radio channel.

Abstract: A method of performing logic synthesis of at least a part of an integrated circuit design. The method comprises identifying a first and at least one further module within the IC design that are mutually exclusive, selecting at least one register element within the first identified module and at least one register element within the at least one further identified module to be shared, and merging the first and at least one further mutually exclusive modules such that at least one common register element is shared between the first and at least one further mutually exclusive modules for the register elements selected to be shared.

Abstract: A method for turbo-encoding a block of data including: receiving data bits of the block of data; masking irrelevant data bits by a masking unit, wherein irrelevant data bits are data bits that regardless of their value do not affect a final state of an interleaved convolutional encoder of a turbo encoder; calculating a last state of the interleaved convolutional encoder based on relevant data bits provided by the masking unit; wherein the calculating of the last state of the interleaved convolutional encoder is initialized before receiving the entire block of data; finding an initial state of the interleaved convolutional encoder based on the last state of the interleaved convolutional encoder; wherein the initial state of the interleaved convolutional encoder equals a final state of the interleaved convolutional encoder; initializing the interleaved convolutional encoder to the initial state; and turbo-encoding the interleaved data bits by the interleaved convolutional encoder.

Abstract: An encoding module comprises an inverse interleaving module arranged to: determine an initial location index within an interleaving matrix for a data bit; and perform bit reverse ordering (BRO) on a column index value for the initial location index for the data bit to obtain a BRO column index value for the data bit. The inverse interleaving module is further arranged to calculate a number of valid interleaving matrix addresses preceding a location index for the data bit following bit reverse ordering; and determine a position of the data bit within the interleaved data stream based on the calculated number of valid addresses.

Abstract: A method for turbo-encoding a block of data including: receiving data bits of the block of data; masking irrelevant data bits by a masking unit, wherein irrelevant data bits are data bits that regardless of their value do not affect a final state of an interleaved convolutional encoder of a turbo encoder; calculating a last state of the interleaved convolutional encoder based on relevant data bits provided by the masking unit; wherein the calculating of the last state of the interleaved convolutional encoder is initialized before receiving the entire block of data; finding an initial state of the interleaved convolutional encoder based on the last state of the interleaved convolutional encoder; wherein the initial state of the interleaved convolutional encoder equals a final state of the interleaved convolutional encoder; initializing the interleaved convolutional encoder to the initial state; and turbo-encoding the interleaved data bits by the interleaved convolutional encoder.

Abstract: An encoding module comprises an inverse interleaving module arranged to: determine an initial location index within an interleaving matrix for a data bit; and perform bit reverse ordering (BRO) on a column index value for the initial location index for the data bit to obtain a BRO column index value for the data bit. The inverse interleaving module is further arranged to calculate a number of valid interleaving matrix addresses preceding a location index for the data bit following bit reverse ordering; and determine a position of the data bit within the interleaved data stream based on the calculated number of valid addresses.