Patents by Inventor Elizabeth Foster
Elizabeth Foster has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8838543Abstract: An archiving system for enabling searching for collections of items is disclosed. A processing unit displays an archived items collection management template in respect of a particular collection of items and prompts a user to complete the template fields with data obtained by the user from manually reviewing that collection of items to capture information relevant to each of the template fields. An archiving controller stores, in pre-determined data fields of a storage area of a data store corresponding to said collection of items, the data from the completed template fields. A document search controller may search the pre-determined data fields of the storage areas of the data store corresponding to each of the collections of items to identify ones of the collection of items which match search criteria.Type: GrantFiled: November 19, 2010Date of Patent: September 16, 2014Assignee: Vodafone IP Licensing LimitedInventors: Gabrielle Sarah Phyo, Nickola John Vidovich, Elizabeth Foster
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Patent number: 7974569Abstract: Computer method and apparatus enable customization of lesson plans per student. The invention method and apparatus include a curriculum data store holding a plurality of curriculum records, a student record data store and a processor routine coupled to the student record data store and the curriculum data store. Each curriculum record indicates a respective teaching activity and implementation details of the activity as part of a lesson plan. There are different activities for different domains. The processor routine enables, for a given student, educator-user selection of a curriculum record with its respective activity, as a function of assessed skill level in a subject domain and/or learning profile of the student. The processor routine generates a custom lesson plan, for the given student, that includes the activity of the user-selected curriculum record. The processor routine may suspend or otherwise hold the custom lesson plan pending supervisory review at various times.Type: GrantFiled: November 17, 2004Date of Patent: July 5, 2011Assignee: The New England Center for Children, Inc.Inventors: Renee Carolyn Mansfield, Laura Larsen Dudley, Karen Theresa DeGregory, Katherine Elizabeth Foster
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Publication number: 20110145202Abstract: An archiving system for enabling searching for collections of items is disclosed. A processing unit displays an archived items collection management template in respect of a particular collection of items and prompts a user to complete the template fields with data obtained by the user from manually reviewing that collection of items to capture information relevant to each of the template fields. An archiving controller stores, in pre-determined data fields of a storage area of a data store corresponding to said collection of items, the data from the completed template fields. A document search controller may search the pre-determined data fields of the storage areas of the data store corresponding to each of the collections of items to identify ones of the collection of items which match search criteria.Type: ApplicationFiled: November 19, 2010Publication date: June 16, 2011Inventors: Gabrielle Sarah Phyo, Nickola John Vidovich, Elizabeth Foster
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Patent number: 7332212Abstract: A method of making a circuitized substrate such as a laminate chip carrier in which a polymer, e.g., Teflon, is used as a dielectric layer and a promotion adhesion layer of a polymer is used to securely adhere a conductive layer thereto which is deposited by plating. The resulting product is thus able to provide extremely narrow conductive circuitry for subsequent connections, e.g., to a semiconductor chip. Electroless plating is the preferred plating method with the dielectric immersed in a solution of conductive monomers, e.g., pyrrole monomer, the solution also possibly containing a seed material such as palladium-tin.Type: GrantFiled: October 5, 2005Date of Patent: February 19, 2008Assignee: Endicott Interconnect Technologies, Inc.Inventors: Elizabeth Foster, Gregory Kevern, Anita Sargent
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Patent number: 7303917Abstract: This invention is directed to a method for the expression of a gene of interest, or a chimeric or modified gene allowing the localization of a protein, protein fusion, peptide or fragment of interest within the extracellular domain of a floral cell. This method comprises preparing a construct comprising a promoter sequence capable of expressing a gene encoding the protein, protein fusion, peptide, or fragment of interest, within the floral cell; a translated sequence of the protein, protein fusion, peptide, or fragment of interest, which is localized within the extracellular domain of a floral cell; a gene that encodes the protein, protein fusion, peptide, or fragment of interest; and a terminator sequence, and transforming a plant. Plants transformed with such a construct are characterized as having a protein, fragment thereof, or peptide of interest on the surface of a floral cell.Type: GrantFiled: December 19, 2002Date of Patent: December 4, 2007Assignee: Her Majesty the Queen in Right of Canada as Represented by the Minister of Agriculture and Agri-Food Eastern Cereal & Oilseed, Research CenterInventors: Laurian S. Robert, Stephen Gleddie, Elizabeth Foster
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Patent number: 7303873Abstract: T-DNA tagging with a promoterless ?-glucuronidase (GUS) gene generated transgenic Nicotiana tabacum plants that expressed GUS activity either only in developing seed coats, or constitutively. Cloning and deletion analysis of the GUS fusion revealed that the promoter responsible for seed coat specificity was located in the plant DNA proximal to the GUS gene. Analysis of the region demonstrated that the seed coat-specificity of GUS expression in this transgenic plant resulted from T-DNA insertion next to a cryptic promoter. This promoter is useful in controlling the expression of genes to the developing seed coat in plant seeds. Similarly, cloning and characterization of the cryptic constitutive promoter revealed the occurrence of several cryptic regulatory regions. These regions include promoter, negative regulatory elements, transcriptional enhancers, core promoter regions, and translational enhancers and other regulatory elements.Type: GrantFiled: May 13, 2003Date of Patent: December 4, 2007Assignee: Her Majesty the Queen in Right of Canada as Represented by the Minister of Agriculture and Agri-FoodInventors: Brian Miki, Thérèse Ouellet, Jiro Hattori, Elizabeth Foster, Hélène Labbé, Teresa Martin-Heller, Lining Tian, Daniel Charles William Brown, Peijun Zhang, Keqiang Wu
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Patent number: 7084509Abstract: The density of electronic packaging and the electrical reliability of the sub-assemblies utilizing stacked blind vias are improved by providing a blind, landless via in a first dielectric layer laminated to a conductive metal core serving as a ground plane or a power plane. A hole is provided through the dielectric layer extending to the core. A metal, such as copper, is deposited electrolytically using the metal core as the cathode, or electrolessly without seeding into the hole. The metal is deposited on the core and progressively builds in the hole to the depth required for the via. A second dielectric layer is laminated to the first, and is provided with a second layer blind via aligned with the first via. This second via may be formed by conventional plating techniques. Multiple dielectric layers with stacked blind vias can be assembled in this manner.Type: GrantFiled: October 3, 2002Date of Patent: August 1, 2006Assignee: International Business Machines CorporationInventors: Frank D. Egitto, Elizabeth Foster, Raymond T. Galasco, Voya R. Markovich, Manh-Quan Tam Nguyen
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Patent number: 7063762Abstract: A method of making a circuitized substrate such as a laminate chip carrier in which a polymer, e.g., Teflon, is used as a dielectric layer and a promotion adhesion layer of a polymer is used to securely adhere a conductive layer thereto which is deposited by plating. The resulting product is thus able to provide extremely narrow conductive circuitry for subsequent connections, e.g., to a semiconductor chip. Electroless plating is the preferred plating method with the dielectric immersed in a solution of conductive monomers, e.g., pyrrole monomer, the solution also possibly containing a seed material such as palladium-tin.Type: GrantFiled: August 20, 2003Date of Patent: June 20, 2006Assignee: Endicott Interconnect Technologies, Inc.Inventors: Elizabeth Foster, Gregory Kevern, Anita Sargent
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Publication number: 20060029781Abstract: A method of making a circuitized substrate such as a laminate chip carrier in which a polymer, e.g., Teflon, is used as a dielectric layer and a promotion adhesion layer of a polymer is used to securely adhere a conductive layer thereto which is deposited by plating. The resulting product is thus able to provide extremely narrow conductive circuitry for subsequent connections, e.g., to a semiconductor chip. Electroless plating is the preferred plating method with the dielectric immersed in a solution of conductive monomers, e.g., pyrrole monomer, the solution also possibly containing a seed material such as palladium-tin.Type: ApplicationFiled: October 5, 2005Publication date: February 9, 2006Applicant: Endicott Interconnect Technologies, Inc.Inventors: Elizabeth Foster, Gregory Kevern, Anita Sargent
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Patent number: 6924224Abstract: The density of electronic packaging and the electrical reliability of the sub-assemblies utilizing stacked blind vias are improved by providing a blind, landless via in a first dielectric layer laminated to a conductive metal core serving as a ground plane or a power plane. A hole is provided through the dielectric layer extending to the core. A metal, such as copper, is deposited electrolytically using the metal core as the cathode, or electrolessly without seeding into the hole. The metal is deposited on the core and progressively builds in the hole to the depth required for the via. A second dielectric layer is laminated to the first, and is provided with a second layer blind via aligned with the first via. This second via may be formed by conventional plating techniques. Multiple dielectric layers with stacked blind vias can be assembled in this manner.Type: GrantFiled: December 5, 2003Date of Patent: August 2, 2005Assignee: International Business Machines CorporationInventors: Frank D. Egitto, Elizabeth Foster, Raymond T. Galasco, Voya R. Markovich, Manh-Quan Tam Nguyen
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Publication number: 20050055742Abstract: An nucleotide sequence and that exhibits regulatory element activity is disclosed. The nucleotide sequence may be defined by SEQ ID NO:22, a nucleotide sequence that hybridizes to the nucleic acid sequence of SEQ ID NO:22, or a compliment thereof. Also disclosed is a chimeric construct comprising the nucleotide sequence operatively linked with a coding region of interest. A method of expressing a coding region of interest within a plant by introducing the chimeric construct described above, into the plant, and expressing the coding region of interest is also provided. Also disclosed are plants, seed, or plant cells comprising the chimeric construct as defined above.Type: ApplicationFiled: June 10, 2004Publication date: March 10, 2005Inventors: Brian Miki, Jiro Hattori, Teresa Martin-Heller, Helene Labbe, Kamal Malik, Elizabeth Foster, Keqiang Wu, Daniel Brown, Lining Tian, Therese Ouellet, Peijun Zhang, Elizabeth James, Pierre Fobert, Venkatram Iyer
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Publication number: 20050039840Abstract: A method of making a circuitized substrate such as a laminate chip carrier in which a polymer, e.g., Teflon, is used as a dielectric layer and a promotion adhesion layer of a polymer is used to securely adhere a conductive layer thereto which is deposited by plating. The resulting product is thus able to provide extremely narrow conductive circuitry for subsequent connections, e.g., to a semiconductor chip. Electroless plating is the preferred plating method with the dielectric immersed in a solution of conductive monomers, e.g., pyrrole monomer, the solution also possibly containing a seed material such as palladium-tin.Type: ApplicationFiled: August 20, 2003Publication date: February 24, 2005Applicant: Endicott Interconnect Technologies, Inc.Inventors: Elizabeth Foster, Gregory Kevern, Anita Sargent
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Patent number: 6843929Abstract: A method and associated structure for increasing the rate at which a chromium volume is etched when the chromium body is contacted by an acid solution such as hydrochloric acid. The etch rate is increased by a metallic or steel body in continuous electrical contact with the chromium volume, both of which are in continuous contact with the acid solution. At a temperature between about 21° C. and about 52° C., and a hydrochloric acid concentration (molarity) between about 1.2 M and about 2.4 M, the etch rate is at least a factor of about two greater than an etch rate that would occur in an absence of the steel body. In one embodiment, the chromium volume is a chromium layer that rests upon a conductive layer that includes a metal such as copper, wherein the acid solution is not in contact with the conductive layer.Type: GrantFiled: February 28, 2000Date of Patent: January 18, 2005Assignee: International Business Machines CorporationInventors: Donald S. Farquhar, Edmond O. Fey, Elizabeth Foster, Michael J. Klodowski, Paul G. Rickerl
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Patent number: 6835533Abstract: A method for fabricating circuitized substrates which reduces shorts, and does not require baking and resulting film. The method employs a photoimageable dielectric film, having a solvent content less than about 5%, and a glass transition temperature, when cured, which is greater than about 110° C. A photoimageable dielectric film is provided having from about 95% to about 100% solids, and comprising: from 0% to about 30% of the solids, of a particulate rheology modifier; from about 70% to about 100% of the solids of an epoxy resin system (liquid at 20° C.) comprising: from about 85% to about 99.9% epoxy resins; and from about 0.1 to 15 parts of the total resin weight, a cationic photoinitiator; from 0% to about 5% solvent; applying the photoimageable dielectric film to a circuitized substrate; and exposing the film to actinic radiation.Type: GrantFiled: February 18, 2004Date of Patent: December 28, 2004Assignee: International Business Machines CorporationInventors: Elizabeth Foster, Gary A. Johansson, Heike Marcello, David J. Russell
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Patent number: 6829823Abstract: A method of making a multi-layered interconnect structure. First and second electrically conductive members are formed on the first and second dielectric layers, respectively. The dielectric layer are formed on opposing surfaces of a thermally conductive layer. A first and second electrically conductive layer is formed within the first dielectric layer. The second electrically conductive layer includes shielded signal conductors and is positioned between the first electrically conductive layer and the thermally conductive layer. A plated through hole (PTH) formed through the interconnect structure is electrically connected to one of the first and second electrically conductive members and to one of the shielded signal conductors.Type: GrantFiled: February 5, 2002Date of Patent: December 14, 2004Assignee: International Business Machines CorporationInventors: Francis J. Downes, Jr., Donald S. Farquhar, Elizabeth Foster, Robert M. Japp, Gerald W. Jones, John S. Kresge, Robert D. Sebesta, David B. Stone, James R. Wilcox
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Patent number: 6784289Abstract: The present invention is directed to translational regulatory elements that mediate the amount of protein produced within a host capable of expressing a construct comprising one or more translational regulatory elements in operative association with a gene of interest. These translational regulatory elements were derived from T1275 (tCUP) and exhibit a high degree of similarity with members of the RENT family of repetitive elements. Translational regulatory elements are disclosed that either increase or decrease he amount of protein produced within the host organism. These translational elements are operative in a wide range of hosts including plant, animals, yeast, fungi and bacteria. Analogs, derivatives and fragments of these translational elements are also disclosed.Type: GrantFiled: December 21, 2000Date of Patent: August 31, 2004Assignee: Her Majesty the Queen in Right of Canada, as represented by the Minister of Agriculture and Agri-FoodInventors: Thérèse Ouellet, Brian M. Miki, Elizabeth Foster, Teresa Martin-Heller, Lining Tian, Daniel C. Brown, Peijun Zhang, Jiro Hattori, Kamal Malik, Keqiang Wu, David A. Theilmann, Raymond Tropiano
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Publication number: 20040161702Abstract: A method for fabricating circuitized substrates which reduces shorts, and does not require baking and resulting film. The method employs a photoimageable dielectric film, having a solvent content less than about 5%, and a glass transition temperature, when cured, which is greater than about 110° C. A photoimageable dielectric film is provided having from about 95% to about 100% solids, and comprising: from 0% to about 30% of the solids, of a particulate rheology modifier; from about 70% to about 100% of the solids of an epoxy resin system (liquid at 20° C.) comprising: from about 85% to about 99.9% epoxy resins; and from about 0.1 to 15 parts of the total resin weight, a cationic photoinitiator; from 0% to about 5% solvent; applying the photoimageable dielectric film to a circuitized substrate; and exposing the film to actinic radiation.Type: ApplicationFiled: February 18, 2004Publication date: August 19, 2004Applicant: International Business Machines CorporationInventors: Elizabeth Foster, Gary A. Johansson, Heike Marcello, David J. Russell
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Publication number: 20040132279Abstract: The density of electronic packaging and the electrical reliability of the sub-assemblies utilizing stacked blind vias are improved by providing a blind, landless via in a first dielectric layer laminated to a conductive metal core serving as a ground plane or a power plane. A hole is provided through the dielectric layer extending to the core. A metal, such as copper, is deposited electrolytically using the metal core as the cathode, or electrolessly without seeding into the hole. The metal is deposited on the core and progressively builds in the hole to the depth required for the via. A second dielectric layer is laminated to the first, and is provided with a second layer blind via aligned with the first via. This second via may be formed by conventional plating techniques. Multiple dielectric layers with stacked blind vias can be assembled in this manner.Type: ApplicationFiled: December 5, 2003Publication date: July 8, 2004Applicant: International Business Machines CorporationInventors: Frank D. Egitto, Elizabeth Foster, Raymond T. Galasco, Voya R. Markovich, Manh-Quan Tam Nguyen
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Publication number: 20040073022Abstract: T-DNA tagging with a promoterless &bgr;-glucuronidase (GUS) gene generated transgenic Nicotiana tabacum plants that expressed GUS activity either only in developing seed coats, or constitutively. Cloning and deletion analysis of the GUS fusion revealed that the promoter responsible for seed coat specificity was located in the plant DNA proximal to the GUS gene. Analysis of the region demonstrated that the seed coat-specificity of GUS expression in this transgenic plant resulted from T-DNA insertion next to a cryptic promoter. This promoter is useful in controlling the expression of genes to the developing seed coat in plant seeds. Similarly, cloning and characterization of the cryptic constitutive promoter revealed the occurrence of several cryptic regulatory regions. These regions include promoter, negative regulatory elements, transcriptional enhancers, core promoter regions, and translational enhancers and other regulatory elements.Type: ApplicationFiled: May 13, 2003Publication date: April 15, 2004Applicant: Her Majesty the Queen in Right of Canada as Rep.by the Minister of Agriculture and Agri-Food CanadaInventors: Brian Miki, Therese Ouellet, Jiro Hattori, Elizabeth Foster, Helene Labbe, Teresa Martin-Heller, Lining Tian, Daniel Charles William Brown, Peijun Zhang, Keqiang Wu
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Publication number: 20040065960Abstract: The density of electronic packaging and the electrical reliability of the sub-assemblies utilizing stacked blind vias are improved by providing a blind, landless via in a first dielectric layer laminated to a conductive metal core serving as a ground plane or a power plane. A hole is provided through the dielectric layer extending to the core. A metal, such as copper, is deposited electrolytically using the metal core as the cathode, or electrolessly without seeding into the hole. The metal is deposited on the core and progressively builds in the hole to the depth required for the via. A second dielectric layer is laminated to the first, and is provided with a second layer blind via aligned with the first via. This second via may be formed by conventional plating techniques. Multiple dielectric layers with stacked blind vias can be assembled in this manner.Type: ApplicationFiled: October 3, 2002Publication date: April 8, 2004Applicant: International Business Machines CorporationInventors: Frank D. Egitto, Elizabeth Foster, Raymond T. Galasco, Voya R. Markovich, Manh-Quan Tam Nguyen