Abstract: A memory interface latch including a data NAND gate and a feedback gate can be created within an integrated circuit (IC). When a feedback node is driven low, the data NAND gate can drive an inverted value of a memory array bitline input to a data output of the memory interface latch within a time of one gate delay. A feedback gate can, in a functional mode, during one phase of a clock signal, drive the feedback node high and during the other phase of the clock signal, drive the feedback node to a complement the data output. The feedback gate can be also, in an LBIST write-through mode, drive the feedback node to the value of a WRITE_DATA input. The feedback gate can be also, in a fence mode, drive the feedback node to fixed logic value.

Abstract: A memory interface latch including a data NAND gate and a feedback gate can be created within an integrated circuit (IC). When a feedback node is driven low, the data NAND gate can drive an inverted value of a memory array bitline input to a data output of the memory interface latch within a time of one gate delay. A feedback gate can, in a functional mode, during one phase of a clock signal, drive the feedback node high and during the other phase of the clock signal, drive the feedback node to a complement the data output. The feedback gate can be also, in an LBIST write-through mode, drive the feedback node to the value of a WRITE_DATA input. The feedback gate can be also, in a fence mode, drive the feedback node to fixed logic value.

Abstract: A memory interface latch including a data NAND gate and a feedback gate can be created within an integrated circuit (IC). When a feedback node is driven low, the data NAND gate can drive an inverted value of a memory array bitline input to a data output of the memory interface latch within a time of one gate delay. A feedback gate can, in a functional mode, during one phase of a clock signal, drive the feedback node high and during the other phase of the clock signal, drive the feedback node to a complement the data output. The feedback gate can be also, in an LBIST write-through mode, drive the feedback node to the value of a WRITE_DATA input. The feedback gate can be also, in a fence mode, drive the feedback node to fixed logic value.

Abstract: A memory interface latch including a data NAND gate and a feedback gate can be created within an integrated circuit (IC). When a feedback node is driven low, the data NAND gate can drive an inverted value of a memory array bitline input to a data output of the memory interface latch within a time of one gate delay. A feedback gate can, in a functional mode, during one phase of a clock signal, drive the feedback node high and during the other phase of the clock signal, drive the feedback node to a complement the data output. The feedback gate can be also, in an LBIST write-through mode, drive the feedback node to the value of a WRITE_DATA input. The feedback gate can be also, in a fence mode, drive the feedback node to fixed logic value.

Abstract: A memory interface latch including a data NAND gate and a feedback gate can be created within an integrated circuit (IC). When a feedback node is driven low, the data NAND gate can drive an inverted value of a memory array bitline input to a data output of the memory interface latch within a time of one gate delay. A feedback gate can, in a functional mode, during one phase of a clock signal, drive the feedback node high and during the other phase of the clock signal, drive the feedback node to a complement the data output. The feedback gate can be also, in an LBIST write-through mode, drive the feedback node to the value of a WRITE_DATA input. The feedback gate can be also, in a fence mode, drive the feedback node to fixed logic value.

Abstract: A climate-controlled vending machine is monitored using data analytics. The climate-controlled vending machine includes a primary storage unit for storing two or more items. A first slot of an item is determined to be available within a secondary storage unit of the climate-controlled vending machine. The secondary storage unit is a climate-controlled unit. A first item, of the two or more items within the primary storage unit, is transferred to the first slot of the secondary storage unit. The first item within the first slot of the secondary storage unit is altered to a first condition. A selection from a first user is received. In response to the reception of the selection of the first item, the first item is dispensed to the user from a dispensary unit, wherein the item is being of the first condition. The first slot is replenished with a replacement item from the primary storage.

Abstract: A climate-controlled vending machine is monitored using data analytics. The climate-controlled vending machine includes a primary storage unit for storing two or more items. A first slot of an item is determined to be available within a secondary storage unit of the climate-controlled vending machine. The secondary storage unit is a climate-controlled unit. A first item, of the two or more items within the primary storage unit, is transferred to the first slot of the secondary storage unit. The first item within the first slot of the secondary storage unit is altered to a first condition. A selection from a first user is received. In response to the reception of the selection of the first item, the first item is dispensed to the user from a dispensary unit, wherein the item is being of the first condition. The first slot is replenished with a replacement item from the primary storage.

Abstract: A climate-controlled vending machine is monitored using data analytics. The climate-controlled vending machine includes a primary storage unit for storing two or more items. A first slot of an item is determined to be available within a secondary storage unit of the climate-controlled vending machine. The secondary storage unit is a climate-controlled unit. A first item, of the two or more items within the primary storage unit, is transferred to the first slot of the secondary storage unit. The first item within the first slot of the secondary storage unit is altered to a first condition. A selection from a first user is received. In response to the reception of the selection of the first item, the first item is dispensed to the user from a dispensary unit, wherein the item is being of the first condition. The first slot is replenished with a replacement item from the primary storage.

Abstract: A climate-controlled vending machine is monitored using data analytics. The climate-controlled vending machine includes a primary storage unit for storing two or more items. A first slot of an item is determined to be available within a secondary storage unit of the climate-controlled vending machine. The secondary storage unit is a climate-controlled unit. A first item, of the two or more items within the primary storage unit, is transferred to the first slot of the secondary storage unit. The first item within the first slot of the secondary storage unit is altered to a first condition. A selection from a first user is received. In response to the reception of the selection of the first item, the first item is dispensed to the user from a dispensary unit, wherein the item is being of the first condition. The first slot is replenished with a replacement item from the primary storage.

Abstract: A method and circuit for implementing sense amplifiers for sensing local write driver with bootstrap write assist for Static Random Access Memory (SRAM) arrays, and a design structure on which the subject circuit resides are provided. The circuit includes a sense amplifier used in both read and write operations with a write assist boost circuitry. The sense amplifier captures and amplifies write data at a selected SRAM cell column and drives the write data onto local bit lines. The write assist boost circuitry temporarily supplies an increased device voltage differential to the SRAM cell during write operations to significantly increase SRAM cell write ability.

Abstract: A method and circuit for implementing sense amplifiers for sensing local write driver with bootstrap write assist for Static Random Access Memory (SRAM) arrays, and a design structure on which the subject circuit resides are provided. The circuit includes a sense amplifier used in both read and write operations with a write assist boost circuitry. The sense amplifier captures and amplifies write data at a selected SRAM cell column and drives the write data onto local bit lines. The write assist boost circuitry temporarily supplies an increased device voltage differential to the SRAM cell during write operations to significantly increase SRAM cell write ability.

Abstract: An SRAM includes a global bit line, an SRAM cell, precharge logic, discharge logic, and sense logic. The SRAM cell stores a first logical value or a second logic value and is coupled to the global bit line. The precharge logic may charge the global bit line to a precharge voltage for a non-read operation and a boosted voltage that is greater than a reference voltage for a read operation. The discharge logic may either maintain the global bit line at the boosted voltage for the first logical value or discharge the global bit line to a discharge voltage that is less than the reference voltage for the second logical value. The sense logic may output the first logical value when the global bit line has the boosted voltage or may output the second logical value when the global bit line has the discharge voltage.

Abstract: An SRAM includes a global bit line, an SRAM cell, precharge logic, discharge logic, and sense logic. The SRAM cell stores a first logical value or a second logic value and is coupled to the global bit line. The precharge logic may charge the global bit line to a precharge voltage for a non-read operation and a boosted voltage that is greater than a reference voltage for a read operation. The discharge logic may either maintain the global bit line at the boosted voltage for the first logical value or discharge the global bit line to a discharge voltage that is less than the reference voltage for the second logical value. The sense logic may output the first logical value when the global bit line has the boosted voltage or may output the second logical value when the global bit line has the discharge voltage.

Abstract: A semiconductor chip and method for diagnostic testing of combinational logic in a logic and array system including Logic Built in Self Test (LBIST) diagnostics are provided. The semiconductor chip includes a logic and array system, an LBIST system, a clocking module, and an addressing module. The method for diagnostic testing includes providing an initialization pattern to an array in the logic and array system, applying a diagnostic control setup, and running the diagnostic test. The diagnostic control setup includes firing a clock every diagnostic test clock cycle and selecting an address from a subset of an address space.

Abstract: An SRAM includes a global bit line, an SRAM cell, precharge logic, discharge logic, and sense logic. The SRAM cell stores a first logical value or a second logic value and is coupled to the global bit line. The precharge logic may charge the global bit line to a precharge voltage for a non-read operation and a boosted voltage that is greater than a reference voltage for a read operation. The discharge logic may either maintain the global bit line at the boosted voltage for the first logical value or discharge the global bit line to a discharge voltage that is less than the reference voltage for the second logical value. The sense logic may output the first logical value when the global bit line has the boosted voltage or may output the second logical value when the global bit line has the discharge voltage.

Abstract: An SRAM includes a global bit line, an SRAM cell, precharge logic, discharge logic, and sense logic. The SRAM cell stores a first logical value or a second logic value and is coupled to the global bit line. The precharge logic may charge the global bit line to a precharge voltage for a non-read operation and a boosted voltage that is greater than a reference voltage for a read operation. The discharge logic may either maintain the global bit line at the boosted voltage for the first logical value or discharge the global bit line to a discharge voltage that is less than the reference voltage for the second logical value. The sense logic may output the first logical value when the global bit line has the boosted voltage or may output the second logical value when the global bit line has the discharge voltage.

Abstract: A method and circuit for implementing low power write disabled local evaluation for Static Random Access Memory (SRAM), and a design structure on which the subject circuit resides are provided. The circuit includes a write disable function to prevent discharge of a global bit line during a write operation. The write disable function disables a NAND gate driving a global pull down device during the write operation preventing the global pull down device from discharging the global bit line.

Abstract: A method and circuit for implementing write assist for Static Random Access Memory (SRAM) arrays, and a design structure on which the subject circuit resides are provided. The circuit includes a write driver including a common bit line supply node, and a common bit line source node. The circuit includes voltage boost circuitry that temporarily boosts the common bit line supply node above supply voltage and temporarily boosts the common bit line source node below source voltage through isolation devices for applying the boosted source and supply voltages to a selected SRAM cell during a write operation. Splitting the boost differential between the common bit lines decreases an overall device voltage differential for providing substantially enhanced reliability of the SRAM array.

Abstract: A method and circuit for implementing write assist for Static Random Access Memory (SRAM) arrays, and a design structure on which the subject circuit resides are provided. The circuit includes a write driver including a common bit line supply node, and a common bit line source node. The circuit includes voltage boost circuitry that temporarily boosts the common bit line supply node above supply voltage and temporarily boosts the common bit line source node below source voltage through isolation devices for applying the boosted source and supply voltages to a selected SRAM cell during a write operation. Splitting the boost differential between the common bit lines decreases an overall device voltage differential for providing substantially enhanced reliability of the SRAM array.

Abstract: A method and circuit for implementing low power write disabled local evaluation for Static Random Access Memory (SRAM), and a design structure on which the subject circuit resides are provided. The circuit includes a write disable function to prevent discharge of a global bit line during a write operation. The write disable function disables a NAND gate driving a global pull down device during the write operation preventing the global pull down device from discharging the global bit line.