Patents by Inventor Elizabeth M. Cooper

Elizabeth M. Cooper has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11119926
    Abstract: Systems, apparatuses, and methods for maintaining a region-based cache directory are disclosed. A system includes multiple processing nodes, with each processing node including a cache subsystem. The system also includes a cache directory to help manage cache coherency among the different cache subsystems of the system. In order to reduce the number of entries in the cache directory, the cache directory tracks coherency on a region basis rather than on a cache line basis, wherein a region includes multiple cache lines. Accordingly, the system includes a region-based cache directory to track regions which have at least one cache line cached in any cache subsystem in the system. The cache directory includes a reference count in each entry to track the aggregate number of cache lines that are cached per region. If a reference count of a given entry goes to zero, the cache directory reclaims the given entry.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: September 14, 2021
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Vydhyanathan Kalyanasundharam, Kevin M. Lepak, Amit P. Apte, Ganesh Balakrishnan, Eric Christopher Morton, Elizabeth M. Cooper, Ravindra N. Bhargava
  • Patent number: 10540316
    Abstract: Systems, apparatuses, and methods for implementing a cancel and replay mechanism for ordered requests are disclosed. A system includes at least an ordering master, a memory controller, a coherent slave coupled to the memory controller, and an interconnect fabric coupled to the ordering master and the coherent slave. The ordering master generates a write request which is forwarded to the coherent slave on the path to memory. The coherent slave sends invalidating probes to all processing nodes and then sends an indication that the write request is globally visible to the ordering master when all cached copies of the data targeted by the write request have been invalidated. In response to receiving the globally visible indication, the ordering master starts a timer. If the timer expires before all older requests have become globally visible, then the write request is cancelled and replayed to ensure forward progress in the fabric and avoid a potential deadlock scenario.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: January 21, 2020
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Vydhyanathan Kalyanasundharam, Eric Christopher Morton, Chen-Ping Yang, Amit P. Apte, Elizabeth M. Cooper
  • Publication number: 20190205280
    Abstract: Systems, apparatuses, and methods for implementing a cancel and replay mechanism for ordered requests are disclosed. A system includes at least an ordering master, a memory controller, a coherent slave coupled to the memory controller, and an interconnect fabric coupled to the ordering master and the coherent slave. The ordering master generates a write request which is forwarded to the coherent slave on the path to memory. The coherent slave sends invalidating probes to all processing nodes and then sends an indication that the write request is globally visible to the ordering master when all cached copies of the data targeted by the write request have been invalidated. In response to receiving the globally visible indication, the ordering master starts a timer. If the timer expires before all older requests have become globally visible, then the write request is cancelled and replayed to ensure forward progress in the fabric and avoid a potential deadlock scenario.
    Type: Application
    Filed: December 28, 2017
    Publication date: July 4, 2019
    Inventors: Vydhyanathan Kalyanasundharam, Eric Christopher Morton, Chen-Ping Yang, Amit P. Apte, Elizabeth M. Cooper
  • Publication number: 20190188137
    Abstract: Systems, apparatuses, and methods for maintaining a region-based cache directory are disclosed. A system includes multiple processing nodes, with each processing node including a cache subsystem. The system also includes a cache directory to help manage cache coherency among the different cache subsystems of the system. In order to reduce the number of entries in the cache directory, the cache directory tracks coherency on a region basis rather than on a cache line basis, wherein a region includes multiple cache lines. Accordingly, the system includes a region-based cache directory to track regions which have at least one cache line cached in any cache subsystem in the system. The cache directory includes a reference count in each entry to track the aggregate number of cache lines that are cached per region. If a reference count of a given entry goes to zero, the cache directory reclaims the given entry.
    Type: Application
    Filed: December 18, 2017
    Publication date: June 20, 2019
    Inventors: Vydhyanathan Kalyanasundharam, Kevin M. Lepak, Amit P. Apte, Ganesh Balakrishnan, Eric Christopher Morton, Elizabeth M. Cooper, Ravindra N. Bhargava
  • Patent number: 10248564
    Abstract: A system and method for network traffic management between multiple nodes are described. A computing system includes multiple nodes connected to one another. When a home node determines a number of nodes requesting read access for a given data block assigned to the home node exceeds a threshold and a copy of the given data block is already stored at a first node of the multiple nodes in the system, the home node sends a command to the first node. The command directs the first node to forward a copy of the given data block to the home node. The home node then maintains a copy of the given data block and forwards copies of the given data block to other requesting nodes until the home node detects a write request or a lock release request for the given data block.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: April 2, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Vydhyanathan Kalyanasundharam, Eric Christopher Morton, Amit P. Apte, Elizabeth M. Cooper
  • Publication number: 20170371787
    Abstract: A system and method for network traffic management between multiple nodes are described. A computing system includes multiple nodes connected to one another. When a home node determines a number of nodes requesting read access for a given data block assigned to the home node exceeds a threshold and a copy of the given data block is already stored at a first node of the multiple nodes in the system, the home node sends a command to the first node. The command directs the first node to forward a copy of the given data block to the home node. The home node then maintains a copy of the given data block and forwards copies of the given data block to other requesting nodes until the home node detects a write request or a lock release request for the given data block.
    Type: Application
    Filed: June 24, 2016
    Publication date: December 28, 2017
    Inventors: Vydhyanathan Kalyanasundharam, Eric Christopher Morton, Amit P. Apte, Elizabeth M. Cooper
  • Patent number: 8935574
    Abstract: An apparatus, processor, and method for synchronizing trace data. A processor includes multiple cores, and each core operates at a different local clock frequency. A global clock is distributed to each core, and a timestamp is generated using the global clock and the local clock. The timestamp and a local clock saturation value are included in each trace entry, and the local clock saturation value is equal to the ratio between the local clock and the global clock. The trace entries from separate cores are time-correlated in a post-processing phase based on the timestamp and local clock saturation values.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: January 13, 2015
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ryan D. Bedwell, Elizabeth M. Cooper, Eric M. Rentschler
  • Patent number: 8683265
    Abstract: An embodiment of an electronic system includes a first electronic module, a second electronic module, a first debug circuit integrated with the first electronic module, a second debug circuit integrated with the second electronic module, and a communications interface between the first debug circuit and the second debug circuit. The first debug circuit is configured to determine that a triggering event has occurred, and to produce a first cross trigger signal on the communications interface in response to determining that the triggering event has occurred. The second debug circuit is configured to detect the first cross trigger signal on the communications interface, and to perform an action in response to detecting the first cross trigger signal.
    Type: Grant
    Filed: December 29, 2010
    Date of Patent: March 25, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Eric M. Rentschler, Steven J. Kommrusch, Elizabeth M. Cooper, Stephen Ennis
  • Publication number: 20130159780
    Abstract: An apparatus, processor, and method for synchronizing trace data. A processor includes multiple cores, and each core operates at a different local clock frequency. A global clock is distributed to each core, and a timestamp is generated using the global clock and the local clock. The timestamp and a local clock saturation value are included in each trace entry, and the local clock saturation value is equal to the ratio between the local clock and the global clock. The trace entries from separate cores are time-correlated in a post-processing phase based on the timestamp and local clock saturation values.
    Type: Application
    Filed: December 16, 2011
    Publication date: June 20, 2013
    Inventors: Ryan D. Bedwell, Elizabeth M. Cooper, Eric M. Rentschler
  • Publication number: 20120146658
    Abstract: An embodiment of an electronic system includes a first electronic module, a second electronic module, a first debug circuit integrated with the first electronic module, a second debug circuit integrated with the second electronic module, and a communications interface between the first debug circuit and the second debug circuit. The first debug circuit is configured to determine that a triggering event has occurred, and to produce a first cross trigger signal on the communications interface in response to determining that the triggering event has occurred. The second debug circuit is configured to detect the first cross trigger signal on the communications interface, and to perform an action in response to detecting the first cross trigger signal.
    Type: Application
    Filed: December 29, 2010
    Publication date: June 14, 2012
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Eric M. Rentschler, Steven J. Kommrusch, Elizabeth M. Cooper, Stephen Ennis
  • Publication number: 20120150474
    Abstract: In an electronic system that includes a plurality of electronic modules and a plurality of debug circuits, each of which is integrated with one of the plurality of electronic modules, a method for performing debug operations is performed by the plurality of debug circuits. The method includes each of the plurality of debug circuits producing a first cross trigger signal on a communications interface between the plurality of debug circuits, where the first cross trigger signal indicates that a triggering event has not occurred. The method further includes each of the plurality of debug circuits determining whether the triggering event has occurred, and in response to determining that the triggering event has occurred, each of the plurality of debug circuits producing a second cross trigger signal on the communications interface, which indicates that the triggering event has occurred.
    Type: Application
    Filed: December 29, 2010
    Publication date: June 14, 2012
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Eric M. Rentschler, Steven J. Kommrusch, Elizabeth M. Cooper, Stephen Ennis
  • Patent number: 8180944
    Abstract: In an embodiment, a system comprises a memory system and a guest interrupt manager. The guest interrupt manager is configured to receive an interrupt message corresponding to an interrupt that is targeted at a guest executable on the system. The guest interrupt manager is configured to record the interrupt in a data structure in the memory system to ensure that the interrupt is delivered to the guest even if the guest is not active in the system at a time that the interrupt message is received.
    Type: Grant
    Filed: November 3, 2009
    Date of Patent: May 15, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Benjamin C. Serebrin, John F Wiederhirn, Elizabeth M. Cooper, Mark D. Hummel
  • Publication number: 20100191888
    Abstract: In an embodiment, a system comprises a memory system and a guest interrupt manager. The guest interrupt manager is configured to receive an interrupt message corresponding to an interrupt that is targeted at a guest executable on the system. The guest interrupt manager is configured to record the interrupt in a data structure in the memory system to ensure that the interrupt is delivered to the guest even if the guest is not active in the system at a time that the interrupt message is received.
    Type: Application
    Filed: November 3, 2009
    Publication date: July 29, 2010
    Inventors: Benjamin C. Serebrin, John F. Wiederhirn, Elizabeth M. Cooper, Mark D. Hummel
  • Patent number: 6047357
    Abstract: A cache memory system includes multiple cache levels arranged in a hierarchical fashion. A data item stored in a higher level cache level is also stored in all lower level caches. The most recent version of a data item is detected during an initial lookup of a higher level cache. The initial lookup of a higher level cache includes a comparison of address bits for the next lower level cache. Thus the most recent version of a data item is able to be detected without additional lookups to the lower level cache.
    Type: Grant
    Filed: January 27, 1995
    Date of Patent: April 4, 2000
    Assignee: Digital Equipment Corporation
    Inventors: Peter J. Bannon, Elizabeth M. Cooper
  • Patent number: 5548553
    Abstract: A semiconductor memory device according to the invention includes a main memory array comprising a plurality of memory sub-arrays. Each of the memory sub-arrays comprises a plurality of columns and at least one redundant column. Each column of the memory sub-array also includes multiplexing means, coupled to the input and output path of the respective column and an input and output path of a neighboring column. In addition, the redundant column is coupled to the input and output path of a neighboring column. In the event that one of the columns of the memory sub-array is defective, the multiplexing means of each of the columns between the defective column and the redundant column acts to couple the input and output paths of that column to the input and output paths of the neighboring column. With such an arrangement, the defective column is bypassed and a memory device capable of operating without defects is provided.
    Type: Grant
    Filed: December 12, 1994
    Date of Patent: August 20, 1996
    Assignee: Digital Equipment Corporation
    Inventors: Elizabeth M. Cooper, Michael Leary