Patents by Inventor Elizabeth Morrow Cooper

Elizabeth Morrow Cooper has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for providing performance data over a debug bus
    Patent number: 10534743
    Abstract: A device and method for providing performance information about a processing device. A stream of performance data is generated by one or more devices whose performance is reflected in the performance data. This performance data stream is then provided to a parallel port for outputting thereof.
    Type: Grant
    Filed: October 16, 2014
    Date of Patent: January 14, 2020
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Elizabeth Morrow Cooper
  • Coherency probe with link or domain indicator
    Patent number: 9507715
    Abstract: A processor includes a set of processing modules, each of the processing modules including a cache and a coherency manager that keeps track of the memory addresses of data stored at the caches of other processing modules. In response to its local cache requesting access to a particular memory address or other triggering event, the coherency manager generates a coherency probe. In the event that the generated coherency probe is targeted to multiple processing modules, the coherency manager includes a set of multicast bits indicating the processing modules whose caches include copies of the data targeted by the multicast probe. A transport switch that connects the processing module to the fabric communicates the coherency probe only to subset of processing modules indicated by the multicast bits.
    Type: Grant
    Filed: October 24, 2014
    Date of Patent: November 29, 2016
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Eric Morton, Patrick Conway, Elizabeth Morrow Cooper, Vydhyanathan Kalyanasundharam
  • COHERENCY PROBE WITH LINK OR DOMAIN INDICATOR
    Publication number: 20160117248
    Abstract: A processor includes a set of processing modules, each of the processing modules including a cache and a coherency manager that keeps track of the memory addresses of data stored at the caches of other processing modules. In response to its local cache requesting access to a particular memory address or other triggering event, the coherency manager generates a coherency probe. In the event that the generated coherency probe is targeted to multiple processing modules, the coherency manager includes a set of multicast bits indicating the processing modules whose caches include copies of the data targeted by the multicast probe. A transport switch that connects the processing module to the fabric communicates the coherency probe only to subset of processing modules indicated by the multicast bits.
    Type: Application
    Filed: October 24, 2014
    Publication date: April 28, 2016
    Inventors: Eric Morton, Patrick Conway, Elizabeth Morrow Cooper, Vydhyanathan Kalyanasundharam
  • METHOD AND APPARATUS FOR PROVIDING PERFORMANCE DATA OVER A DEBUG BUS
    Publication number: 20150120970
    Abstract: A device and method for providing performance information about a processing device. A stream of performance data is generated by one or more devices whose performance is reflected in the performance data. This performance data stream is then provided to a parallel port for outputting thereof.
    Type: Application
    Filed: October 16, 2014
    Publication date: April 30, 2015
    Inventor: Elizabeth Morrow Cooper