Patents by Inventor Elizabeth SPEECHLEY

Elizabeth SPEECHLEY has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10971550
    Abstract: A technique comprising: forming on a support film a first stack of layers defining an array of photodiodes; forming over the first stack of layers in situ on the support film a second stack of layers defining electrical circuitry by which the photoresponse of each photodiode is independently detectable via an array of conductors outside the array of photodiodes; wherein forming the first stack of layers comprises depositing an organic semiconductor material over a first electrode, and depositing a second electrode over the organic semiconductor material, wherein the electrical circuitry comprises transistors including photosensitive semiconductor channels, and the second electrode also functions to substantially block the incidence of light on the photosensitive semiconductor channels from the direction of the support film.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: April 6, 2021
    Assignee: Flexenable Limited
    Inventors: Guillaume Fichet, Elizabeth Speechley
  • Publication number: 20200328364
    Abstract: A technique comprising: forming a conductor layer in contact with a dielectric layer; patterning the conductor layer using an acidic patterning agent to form a source-drain conductor pattern for one or more transistors at a surface of a workpiece; and forming an organic semiconductor layer over the surface of the workpiece to provide one or more semiconductor channels for the one or more transistors; wherein the method further comprises: prior to forming the conductor layer, treating the dielectric layer with an alkaline agent.
    Type: Application
    Filed: April 9, 2020
    Publication date: October 15, 2020
    Inventors: Guillaume Fichet, Rebekka Willcocks, Elizabeth Speechley
  • Patent number: 10763436
    Abstract: A technique, comprising: forming a stack comprising a semiconductor layer for providing the semiconductor channels of one or more transistors, and an insulator layer; and patterning the stack so as to form in a single process both: (i) one or more interconnection holes for connecting a conductor level on one side of the stack to a conductor level on the opposite side of the stack; and (ii) one or more leakage reduction trenches for reducing leakage paths via the semiconductor between conductor elements on one side of the stack.
    Type: Grant
    Filed: February 9, 2017
    Date of Patent: September 1, 2020
    Assignee: FLEXENABLE LIMITED
    Inventor: Elizabeth Speechley
  • Publication number: 20200203433
    Abstract: A technique comprising: forming on a support film a first stack of layers defining an array of photodiodes; forming over the first stack of layers in situ on the support film a second stack of layers defining electrical circuitry by which the photoresponse of each photodiode is independently detectable via an array of conductors outside the array of photodiodes; wherein forming the first stack of layers comprises depositing an organic semiconductor material over a first electrode, and depositing a second electrode over the organic semiconductor material, wherein the electrical circuitry comprises transistors including photosensitive semiconductor channels, and the second electrode also functions to substantially block the incidence of light on the photosensitive semiconductor channels from the direction of the support film.
    Type: Application
    Filed: December 18, 2019
    Publication date: June 25, 2020
    Inventors: Guillaume Fichet, Elizabeth Speechley
  • Publication number: 20190013472
    Abstract: A technique, comprising: forming a stack comprising a semiconductor layer for providing the semiconductor channels of one or more transistors, and an insulator layer; and patterning the stack so as to form in a single process both: (i) one or more interconnection holes for connecting a conductor level on one side of the stack to a conductor level on the opposite side of the stack; and (ii) one or more leakage reduction trenches for reducing leakage paths via the semiconductor between conductor elements on one side of the stack.
    Type: Application
    Filed: February 9, 2017
    Publication date: January 10, 2019
    Applicant: FLEXENABLE LIMITED
    Inventor: Elizabeth SPEECHLEY