Patents by Inventor Ellen Cheng

Ellen Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for manufacturing transistor
    Patent number: 6555425
    Abstract: A method of manufacturing a transistor. The method comprising the steps of providing a substrate. The substrate comprises a gate oxide layer formed thereon, a polysilicon layer formed on the gate oxide layer, an offset spacer formed on a sidewall of the polysilicon layer and the gate oxide layer and a source/drain formed in the substrate. A conformal dielectric layer is formed over the polysilicon layer, the offset spacer and the source/drain. A spacer is formed on the sidewall of a portion of the conformal dielectric layer over the offset spacer. A portion of the conformal dielectric layer is removed to expose the polysilicon layer and the source/drain. A selective epitaxial growth process is performed to form an epitaxial layer on the polysilicon layer and the source/drain. A portion of the epitaxial layer on the polysilicon layer, the polysilicon layer and the gate oxide layer together form a T-type gate structure.
    Type: Grant
    Filed: June 12, 2001
    Date of Patent: April 29, 2003
    Assignee: United Microelectronics Corp.
    Inventors: Kuo-Tai Huang, Ellen Cheng
  • Method for manufacturing transistor
    Publication number: 20020182799
    Abstract: A method of manufacturing a transistor. The method comprising the steps of providing a substrate. The substrate comprises a gate oxide layer formed thereon, a polysilicon layer formed on the gate oxide layer, an offset spacer formed on a sidewall of the polysilicon layer and the gate oxide layer and a source/drain formed in the substrate. A conformal dielectric layer is formed over the polysilicon layer, the offset spacer and the source/drain. A spacer is formed on the sidewall of a portion of the conformal dielectric layer over the offset spacer. A portion of the conformal dielectric layer is removed to expose the polysilicon layer and the source/drain. A selective epitaxial growth process is performed to form an epitaxial layer on the polysilicon layer and the source/drain. A portion of the epitaxial layer on the polysilicon layer, the polysilicon layer and the gate oxide layer together form a T-type gate structure.
    Type: Application
    Filed: June 12, 2001
    Publication date: December 5, 2002
    Inventors: Kuo-Tai Huang, Ellen Cheng