Abstract: A multi-link interprocessor communication protocol that allows a pair of processors to increase the speed of their communication by using multiple physical links in parallel. When a message is sent from one processor to another, the message is packetized into smaller segments and loaded onto the available physical links according to a simple algorithm. The individual packets are received at the other end, their accurate transmission verified, and the received packets are then reassembled in the proper order. Packets of one or more messages to the same destination can go over the same physical link, or over different physical links; that is, there is no association of any message to any particular physical communication link. Packets received out of order on a per logical channel basis are stored until a correct sequence of packets is received after which their transmission to the message destination is effected.