Patents by Inventor Ellen S. Tormey

Ellen S. Tormey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220119315
    Abstract: LTCC devices are produced from dielectric compositions include a mixture of precursor materials that, upon firing, forms a dielectric material having a magnesium-silicon oxide host. An associated Ag system for LTCC conductors is also described.
    Type: Application
    Filed: February 4, 2021
    Publication date: April 21, 2022
    Inventors: Ellen S. Tormey, Peter Marley, Chao Ma, John Maloney, Yi Yang, Orville W. Brown, Srinivasan Sridharan
  • Patent number: 10625356
    Abstract: A thermal managing electrical connection tape includes a carrier film and a composition including solder powder, with the composition being applied to the carrier film. The composition includes a soldering flux having the solder powder disposed therein. The composition contains between about 50 wt % and about 70 wt % soldering flux. The composition further contains between about 30 wt % and about 50 wt % solder powder. A method of fabricating a thermal managing electrical connection tape includes providing a composition including at least one of a soldering flux and epoxy and/or acrylic, adding a solder powder to the composition, casting the composition on a carrier film, drying the carrier film in a drying furnace to form a dried tape, and cutting the dried tape to a desired width to form a thermal managing electrical connection tape.
    Type: Grant
    Filed: February 10, 2016
    Date of Patent: April 21, 2020
    Assignee: ALPHA ASSEMBLY SOLUTIONS INC.
    Inventors: Steven Dane Prokopiak, Sanyogita Arora, Ranjit S. Pandher, Ellen S. Tormey, Bawa Singh
  • Patent number: 10562809
    Abstract: A low K value, high Q value, low firing dielectric material and method of forming a fired dielectric material. The dielectric material can be fired below 950° C. or below 1100° C., has a K value of less than about 8 at 10-30 GHz and a Q value of greater than 500 or greater than 1000 at 10-30 GHz. The dielectric material includes, before firing a solids portion including 10-95 wt % or 10-99 wt % silica powder and 5-90 wt % or 1-90 wt % glass component. The glass component includes 50-90 mole % SiO2, 5-35 mole % or 0.1-35 mole % B2O3, 0.1-10 mole % or 0.1-25 mole % Al2O3, 0.1-10 mole % K2O, 0.1-10 mole % Na2O, 0.1-20 mole % Li2O, 0.1-30 mole % F. The total amount of Li2O+Na2O+K2O is 0.1-30 mole % of the glass component. The silica powder can be amorphous or crystalline.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: February 18, 2020
    Assignee: Ferro Corporation
    Inventors: Cody J. Gleason, John J. Maloney, Srinivasan Sridharan, George E. Sakoske, Peter Marley, Mohammed H. Megherhi, Yie-Shein Her, Orville W. Brown, Jackie D. Davis, Thomas J. Coffey, Ellen S. Tormey, Stanley Wang, David L. Widlewski
  • Patent number: 10465295
    Abstract: A jettable etchant composition includes 1 to 90 wt % active ingredient, and a remainder containing any combination of the following: 10 to 90 wt % solvent, 0 to 10 wt % reducing agents, <1 to 20 wt % pickling agent, 0 to 5 wt % surfactant, and 0 to 5 wt % antifoam agent. The composition can also include a soluble compound containing at least one element which when dissolved has a higher standard electrode potential than a metal to be etched or a soluble compound containing a group IA element, and a soluble platinum group metal. An ink composition can include a group VA compound or a group IIIA compound in a solvent system formulated to be jettable on a surface at a drop volume of about 5 to about 10 picoliters and to achieve a final sheet resistance of less than about 20 ?/? of the surface upon activation.
    Type: Grant
    Filed: May 19, 2015
    Date of Patent: November 5, 2019
    Assignee: Alpha Assembly Solutions Inc.
    Inventors: Steven Prokopiak, Ellen S. Tormey, Oscar Khaselev, Michael T. Marczi, Bawa Singh
  • Publication number: 20190135683
    Abstract: A low K value, high Q value, low firing dielectric material and method of forming a fired dielectric material. The dielectric material can be fired below 950° C. or below 1100° C., has a K value of less than about 8 at 10-30 GHz and a Q value of greater than 500 or greater than 1000 at 10-30 GHz. The dielectric material includes, before firing a solids portion including 10-95 wt % or 10-99 wt % silica powder and 5-90 wt % or 1-90 wt % glass component. The glass component includes 50-90 mole % SiO2, 5-35 mole % or 0.1-35 mole % B2O3, 0.1-10 mole % or 0.1-25 mole % Al2O3, 0.1-10 mole % K2O, 0.1-10 mole % Na2O, 0.1-20 mole % Li2O, 0.1-30 mole % F. The total amount of Li2O+Na2O+K2O is 0.1-30 mole % of the glass component. The silica powder can be amorphous or crystalline.
    Type: Application
    Filed: November 5, 2018
    Publication date: May 9, 2019
    Inventors: Cody J. Gleason, John J. Maloney, Srinivasan Sridharan, George E. Sakoske, Peter Marley, Mohammed H. Megherhi, Yie-Shein Her, Orville W. Brown, Jackie D. Davis, Thomas J. Coffey, Ellen S. Tormey, Stanley Wang, David L. Widlewski
  • Publication number: 20180036818
    Abstract: A thermal managing electrical connection tape includes a carrier film and a composition including solder powder, with the composition being applied to the carrier film. The composition includes a soldering flux having the solder powder disposed therein. The composition contains between about 50 wt % and about 70 wt % soldering flux. The composition further contains between about 30 wt % and about 50 wt % solder powder. A method of fabricating a thermal managing electrical connection tape includes providing a composition including at least one of a soldering flux and epoxy and/or acrylic, adding a solder powder to the composition, casting the composition on a carrier film, drying the carrier film in a drying furnace to form a dried tape, and cutting the dried tape to a desired width to form a thermal managing electrical connection tape.
    Type: Application
    Filed: February 10, 2016
    Publication date: February 8, 2018
    Inventors: Steven Dane Prokopiak, Sanyogita Arora, Ranjit S. Pandher, Ellen S. Tormey, Bawa Singh
  • Publication number: 20180020554
    Abstract: A method of assembling components, such as electronic components, onto a substrate, such as an electronic substrate, includes applying solder paste to an electronic substrate to form a solder paste deposit, placing a low temperature preform in the solder paste deposit, processing the electronic substrate at a reflow temperature of the solder paste to create a low temperature solder joint, and processing the low temperature solder joint at a reflow temperature that is lower than the reflow temperature of the solder paste. Other methods of assembling components and solder joint compositions are further disclosed.
    Type: Application
    Filed: September 27, 2017
    Publication date: January 18, 2018
    Inventors: Paul Joseph Koep, Ellen S. Tormey, Girard Sidone
  • Patent number: 9801285
    Abstract: A method of assembling components, such as electronic components, onto a substrate, such as an electronic substrate, includes applying solder paste to an electronic substrate to form a solder paste deposit, placing a low temperature preform in the solder paste deposit, processing the electronic substrate at a reflow temperature of the solder paste to create a low temperature solder joint, and processing the low temperature solder joint at a reflow temperature that is lower than the reflow temperature of the solder paste. Other methods of assembling components and solder joint compositions are further disclosed.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: October 24, 2017
    Inventors: Paul Joseph Koep, Ellen S. Tormey, Girard Sidone
  • Publication number: 20170204523
    Abstract: A jettable etchant composition includes 1 to 90 wt % active ingredient, and a remainder containing any combination of the following: 10 to 90 wt % solvent, 0 to 10 wt % reducing agents, <1 to 20 wt % pickling agent, 0 to 5 wt % surfactant, and 0 to 5 wt % antifoam agent. The composition can also include a soluble compound containing at least one element which when dissolved has a higher standard electrode potential than a metal to be etched or a soluble compound containing a group IA element, and a soluble platinum group metal. An ink composition can include a group VA compound or a group IIIA compound in a solvent system formulated to be jettable on a surface at a drop volume of about 5 to about 10 picoliters and to achieve a final sheet resistance of less than about 20 ?/? of the surface upon activation.
    Type: Application
    Filed: May 19, 2015
    Publication date: July 20, 2017
    Inventors: Steven PROKOPIAK, Ellen S. TORMEY, Oscar KHASELEV, Michael T. MARCZI, Bawa SINGH
  • Publication number: 20150078810
    Abstract: A method of assembling components, such as electronic components, onto a substrate, such as an electronic substrate, includes applying solder paste to an electronic substrate to form a solder paste deposit, placing a low temperature preform in the solder paste deposit, processing the electronic substrate at a reflow temperature of the solder paste to create a low temperature solder joint, and processing the low temperature solder joint at a reflow temperature that is lower than the reflow temperature of the solder paste. Other methods of assembling components and solder joint compositions are further disclosed.
    Type: Application
    Filed: March 15, 2013
    Publication date: March 19, 2015
    Inventors: Paul Joseph Koep, Ellen S. Tormey, Girard Sidone
  • Publication number: 20140328039
    Abstract: In accordance with one or more aspects, a method of reducing void formation in a solder joint may comprise applying a solder paste deposit to a substrate, placing a solder preform in the solder paste deposit, disposing a device on the solder preform and the solder paste deposit, and processing the solder paste deposit and the solder preform to form the solder joint between the device and the substrate. In some aspects, the substrate is a printed circuit board and the device is an integrated circuit package.
    Type: Application
    Filed: September 25, 2012
    Publication date: November 6, 2014
    Inventors: Paul J. Koep, Michiel A. de Monchy, Ellen S. Tormey
  • Patent number: 8192047
    Abstract: The present invention relates to an LED lighting system producing light having improved Color Rendering Index (CRI). The system includes a plurality of LEDs wherein the LEDs have at least a first and second characteristic wavelength, and a mixed phosphor layer overlying at least one of a portion of the plurality of LEDs, the phosphor layer absorbing at least a portion of the LED-emitted light and producing phosphor-emitted light, wherein the phosphors includes a third characteristic wavelength and a fourth characteristic wavelength, wherein the third characteristic wavelength and fourth characteristic wavelength are not the same.
    Type: Grant
    Filed: February 15, 2008
    Date of Patent: June 5, 2012
    Assignee: Lighting Science Group Corporation
    Inventors: Edward Bailey, Ellen S. Tormey
  • Publication number: 20100118510
    Abstract: The present invention relates to an LED lighting system producing light having improved Color Rendering Index (CRI). The system includes a plurality of LEDs wherein the LEDs have at least a first and second characteristic wavelength, and a mixed phosphor layer overlying at least one of a portion of the plurality of LEDs, the phosphor layer absorbing at least a portion of the LED-emitted light and producing phosphor-emitted light, wherein the phosphors includes a third characteristic wavelength and a fourth characteristic wavelength, wherein the third characteristic wavelength and fourth characteristic wavelength are not the same.
    Type: Application
    Filed: February 15, 2008
    Publication date: May 13, 2010
    Applicant: LIGHTING SCIENCE GROUP CORPORATION
    Inventors: Edward Bailey, Ellen S. Tormey
  • Patent number: 6191934
    Abstract: High dielectric constant capacitors are made from a dielectric ink of lead-magnesium-niobate and lead oxide powders. Dielectric inks are made by mixing the dielectric powders with a suitable organic vehicle which can be used to coat one or more glass-based green tapes. Buried capacitors are made by coating an overlying and an underlying green tape with a conductor such as silver. Capacitors can also be made by adjusting the organic vehicle and forming a green tape from the dielectric powders. These dielectric green tapes each can be coated with a conductive layer and stacked, the conductive layers connected in parallel. The resultant multilayer capacitors have a very high dielectric constant, while eliminating the need for very large area capacitors, as compared to single layer capacitors.
    Type: Grant
    Filed: December 14, 1998
    Date of Patent: February 20, 2001
    Assignees: Sarnoff Corporation & Co., Ltd., Daewoo Electronics Co., Ltd.
    Inventors: Michael James Liberatore, Attiganal Narayanaswamy Sreeram, Ashok Narayan Prabhu, In-Tae Kim, Je-Do Mun, Sung-Dae Park, Yun-Hwi Park, Joo-Dong Yu, Ellen S. Tormey
  • Patent number: 5514451
    Abstract: Conductive via fill inks for green tapes to be stacked and bonded to a support substrate, the glass used for the green tape having a firing temperature from 850.degree.-950.degree. C., wherein the glass used for the via fill ink has a glass transition temperature that is higher than that of the glass used to make the green tape, preferably does not crystallize at the maximum firing temperature of the green tape and comprises from 30-75 percent by volume of the glass-conductive metal powder mixture of the via fill ink. These conductive via fill inks will not shrink until the green tape shrinkage has commenced during firing of the composite circuit board and they will flow slightly during firing, forming good bonds to the glass in the walls of the vias, thereby ensuring good integrity of the vias and good connections to the circuitry on the fired ceramic multilayer circuit board.
    Type: Grant
    Filed: January 27, 1995
    Date of Patent: May 7, 1996
    Assignee: David Sarnoff Research Center, Inc.
    Inventors: Ananda H. Kumar, Barry J. Thaler, Ashok N. Prabhu, Ellen S. Tormey
  • Patent number: 4769294
    Abstract: Substrates consisting of at least 98% narrow size distribution ceramic particles are co-sinterable with metallized paste to which selected compositions of glass have been added. Substrates produced in accordance with the present invention exhibit superior thermal conductivity, low shrinkage variability, and smoother and more homogeneous surface finish.
    Type: Grant
    Filed: November 26, 1986
    Date of Patent: September 6, 1988
    Assignee: Ceramics Process Systems Corp.
    Inventors: Eric A. Barringer, Roger S. Lind, Charles E. Swain, Ellen S. Tormey