Patents by Inventor Ellery Cochell

Ellery Cochell has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11916552
    Abstract: Techniques and apparatus for dynamically modifying a kernel (and associated user-specified circuitry) for a dynamic region of a programmable integrated circuit (IC) without affecting (e.g., while allowing) operation of other kernels ((and other associated user-specified circuitry) in the programmable IC. Dynamically modifying a kernel may include, for example, unloading an existing kernel, loading a new kernel, or replacing a first kernel with a second kernel). In the case of networking (e.g., in a data center application) where the programmable IC may be part of a hardware acceleration card (e.g., a network interface card (NIC)), the kernel may be user code referred to as a “plugin.
    Type: Grant
    Filed: March 9, 2022
    Date of Patent: February 27, 2024
    Assignee: XILINX, INC.
    Inventors: Ellery Cochell, Ripduman Singh Sohan, Kieran Mansley
  • Publication number: 20230291406
    Abstract: Techniques and apparatus for dynamically modifying a kernel (and associated user-specified circuitry) for a dynamic region of a programmable integrated circuit (IC) without affecting (e.g., while allowing) operation of other kernels ((and other associated user-specified circuitry) in the programmable IC. Dynamically modifying a kernel may include, for example, unloading an existing kernel, loading a new kernel, or replacing a first kernel with a second kernel). In the case of networking (e.g., in a data center application) where the programmable IC may be part of a hardware acceleration card (e.g., a network interface card (NIC)), the kernel may be user code referred to as a “plugin.
    Type: Application
    Filed: March 9, 2022
    Publication date: September 14, 2023
    Inventors: Ellery COCHELL, Ripduman Singh SOHAN, Kieran MANSLEY
  • Patent number: 11144652
    Abstract: Secure updating of programmable integrated circuits includes receiving, within the programmable integrated circuit, a configuration bitstream, inserting, using a processor of the programmable integrated circuit, a key into the configuration bitstream resulting in a modified configuration bitstream, encrypting, using the programmable integrated circuit, the modified configuration bitstream using the key resulting in an encrypted configuration bitstream, and storing the encrypted configuration bitstream in a boot memory for the programmable integrated circuit.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: October 12, 2021
    Assignee: Xilinx, Inc.
    Inventors: Ellery Cochell, Brian S. Martin, Ravi N. Kurlagunda
  • Patent number: 11055106
    Abstract: Bootstrapping a programmable integrated circuit (IC) based network interface card (NIC) can include implementing, within the programmable IC, a first circuitry by loading a first stage configuration bitstream, wherein the first circuitry includes a bus endpoint configured to communicate with a host computer via a communication bus, a platform processor, and a first bootloader. The platform processor, executing the first bootloader, loads a first firmware within the programmable IC. A second circuitry is implemented within the programmable IC by the platform processor executing the first firmware to load a second stage configuration bitstream. The second circuitry includes a NIC controller. The platform processor, executing the first firmware, loads a second firmware within the programmable IC. The second firmware is executable to configure the second circuitry.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: July 6, 2021
    Assignee: Xilinx, Inc.
    Inventors: Ellery Cochell, Brian S. Martin, Chandrasekhar S. Thyamagondlu, Ravi N. Kurlagunda
  • Patent number: 10990547
    Abstract: A device includes a platform implemented, at least in part, in a static region of programmable circuitry and a dynamic region of programmable circuitry configured to implement user-specified circuitry in communication with the platform. The platform is configured to establish and maintain a first communication link with a host data processing system and a second communication link with a network while at least a portion of the dynamic region of programmable circuitry is dynamically reconfigured.
    Type: Grant
    Filed: August 11, 2019
    Date of Patent: April 27, 2021
    Assignee: Xilinx, Inc.
    Inventors: Chandrasekhar S. Thyamagondlu, Ravi Sunkavalli, Ravi N. Kurlagunda, Ellery Cochell
  • Publication number: 20210042252
    Abstract: A device includes a platform implemented, at least in part, in a static region of programmable circuitry and a dynamic region of programmable circuitry configured to implement user-specified circuitry in communication with the platform. The platform is configured to establish and maintain a first communication link with a host data processing system and a second communication link with a network while at least a portion of the dynamic region of programmable circuitry is dynamically reconfigured.
    Type: Application
    Filed: August 11, 2019
    Publication date: February 11, 2021
    Applicant: Xilinx, Inc.
    Inventors: Chandrasekhar S. Thyamagondlu, Ravi Sunkavalli, Ravi N. Kurlagunda, Ellery Cochell
  • Patent number: 10705993
    Abstract: An integrated circuit (IC) can include a command queue having a plurality of slots corresponding to commands from a host processor for execution by a plurality of compute units of the IC and a command request register having a plurality of locations corresponding to the plurality of slots in the command queue. The command request register is configured to generate an interrupt indicating a new command stored within the command queue. The IC can include a controller configured to, in response to the interrupt from the command request register, determine a selected compute unit that is idle from the plurality of compute units to execute the new command. The IC can also include a compute unit direct memory access circuit configured to provide the new command to the available compute unit.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: July 7, 2020
    Assignee: Xilinx, Inc.
    Inventors: Soren T. Soe, Idris I. Tarwala, Ellery Cochell
  • Publication number: 20200159680
    Abstract: An integrated circuit (IC) can include a command queue having a plurality of slots corresponding to commands from a host processor for execution by a plurality of compute units of the IC and a command request register having a plurality of locations corresponding to the plurality of slots in the command queue. The command request register is configured to generate an interrupt indicating a new command stored within the command queue. The IC can include a controller configured to, in response to the interrupt from the command request register, determine a selected compute unit that is idle from the plurality of compute units to execute the new command. The IC can also include a compute unit direct memory access circuit configured to provide the new command to the available compute unit.
    Type: Application
    Filed: November 19, 2018
    Publication date: May 21, 2020
    Applicant: Xilinx, Inc.
    Inventors: Soren T. Soe, Idris I. Tarwala, Ellery Cochell
  • Patent number: 9935637
    Abstract: A design environment for FPGA applications enables configuration of an FPGA platform to include a user design and one or more interface units, which the user design can use to access one or more external modules/devices without needing any particular knowledge of the structure and operation of such modules/devices. The interface unit corresponding to an external device/module, under the control of an operating environment, can establish a communication between the user design and the external module/device. An external processing module can use an interface unit to monitor and/or control a user design.
    Type: Grant
    Filed: February 11, 2015
    Date of Patent: April 3, 2018
    Assignee: NATIONAL INSTRUMENTS CORPORATION
    Inventors: Chen Chang, Kevin B. Camera, Alexander Williams, Brian Jenkins, Ellery Cochell, Robert W. Brodersen, John C. Wawrzynek
  • Publication number: 20150229310
    Abstract: A design environment for FPGA applications enables configuration of an FPGA platform to include a user design and one or more interface units, which the user design can use to access one or more external modules/devices without needing any particular knowledge of the structure and operation of such modules/devices. The interface unit corresponding to an external device/module, under the control of an operating environment, can establish a communication between the user design and the external module/device. An external processing module can use an interface unit to monitor and/or control a user design.
    Type: Application
    Filed: February 11, 2015
    Publication date: August 13, 2015
    Inventors: Chen Chang, Kevin B. Camera, Alexander Williams, Brian Jenkins, Ellery Cochell, Robert W. Brodersen, John C. Wawrzynek