Abstract: A structure and method are disclosed which allow for a more efficient use of silicon in a wafer fabrication process. In accordance with the present invention, the layout of masks used in the fabrication of circuit dice is modified by re-configuring the operating protocol of the stepper such that the alignment keys and targets are formed in the two subfields lying in the upper-left and upper-right corners, respectively, of each field. Thus, the 200 .mu.m-wide portion of each field previously used for alignment (i.e., alignment scribe line 34 of FIG. 2) may now contain patterns used in the formation of circuit dice, thereby increasing the amount of usable surface area on the associated underlying wafer. The operating protocol is further modified such that scribe lines separating rows and columns of subfields are less than 100 .mu.