Abstract: A method includes applying a polymer to a mold, the mold having microstructures with the polymer flowing into the microstructures when applied to the mold. The method includes pressing an inorganic substrate onto the polymer. The method includes curing the polymer to fix the polymer to the inorganic substrate to form an optical element from the polymer and the inorganic substrate, the optical element having microstructures formed by the microstructures in the mold. The method includes releasing the optical element from the mold.

Abstract: A LiDAR system includes alight emitter, a light detector, and a controller.

Abstract: A LiDAR system includes alight emitter, a light detector, and a controller. The controller is programmed to: activate the light emitter to emit a series of shots into a field of view of the light detector; activate the light detector to detect shots reflected from an object in the field of view; determine the size of a subset of the series of shots to be recorded based on a distance of the object from the light detector; and record the subset of the series of shots.

Abstract: A focal-plane array includes an array of pixels. Each pixel includes an avalanche-type diode on a first layer, a read-out circuit (ROIC) on a second layer, and a power-supply circuit on a middle layer stacked between the first layer and the second layer. Since each pixel includes the avalanche-type diode, the ROIC, and the power-supply circuit on different layers circuitry for each pixel is in a top-down footprint of the pixel. Thus a consistent bias voltage to each pixel, decouples the avalanche-type diodes of the different pixels to eliminate crosstalk between adjacent pixels, and allows for individual control of each pixel.

Abstract: A focal-plane array includes an array of pixels. Each pixel includes an avalanche-type diode on a first layer, a read-out circuit (ROIC) on a second layer, and a power-supply circuit on a middle layer stacked between the first layer and the second layer. Since each pixel includes the avalanche-type diode, the ROIC, and the power-supply circuit on different layers circuitry for each pixel is in a top-down footprint of the pixel. Thus a consistent bias voltage to each pixel, decouples the avalanche-type diodes of the different pixels to eliminate crosstalk between adjacent pixels, and allows for individual control of each pixel.

Abstract: A Lidar system includes a focal-plane array having a plurality of pixels. Each pixel includes a first single-photon avalanche diode (SPAD) and a second SPAD. The Lidar system operates by, for each of a plurality of the pixels, applying a bias voltage to the first SPAD of the pixel while no bias voltage or low bias voltage is applied to the second SPAD of the pixel, then removing the bias voltage from the first SPAD of the pixel and applying a bias voltage to the second SPAD of the pixel while no bias voltage or low bias voltage is applied to the first SPAD of the pixel, and then recording detection of a photon by the first SPAD of the pixel and detection of a photon by the second SPAD on a common memory bank of the pixel.

Abstract: A method includes applying a polymer to a mold, the mold having microstructures with the polymer flowing into the microstructures when applied to the mold. The method includes pressing an inorganic substrate onto the polymer. The method includes curing the polymer to fix the polymer to the inorganic substrate to form an optical element from the polymer and the inorganic substrate, the optical element having microstructures formed by the microstructures in the mold. The method includes releasing the optical element from the mold.

Abstract: A semiconductor device includes a first transistor element having a first channel region and a second transistor element having a second channel region, wherein the first channel region includes a first crystalline silicon/germanium (Si/Ge) material mixture having a first germanium concentration, and wherein the second channel region includes a second crystalline Si/Ge material mixture having a second germanium concentration that is higher than the first germanium concentration.

Abstract: A device including an SOI substrate and an isolation structure positioned at least partially in a trench that extends through a buried insulation layer and into a semiconductor bulk substrate of the SOI substrate is disclosed. The isolation structure includes a first dielectric layer positioned in a lower portion of the trench, a first material layer positioned above the first dielectric layer, the first material layer having a material different from a material of the first dielectric layer, and a second dielectric layer positioned above the first material layer, the second dielectric layer having a material different from the material of the first material layer.

Abstract: One illustrative device disclosed herein is formed on an SOI substrate. The transistor device includes a first channel region formed in a semiconductor bulk substrate of the SOI substrate and a first gate insulation layer formed above the first channel region. In one embodiment, the first gate insulation layer includes a part of the buried insulation layer of the SOI substrate and an oxidized part of the semiconductor layer of the SOI substrate.

Abstract: A device including an SOI substrate and an isolation structure positioned at least partially in a trench that extends through a buried insulation layer and into a semiconductor bulk substrate of the SOI substrate is disclosed. The isolation structure includes a first dielectric layer positioned in a lower portion of the trench, a first material layer positioned above the first dielectric layer, the first material layer having a material different from a material of the first dielectric layer, and a second dielectric layer positioned above the first material layer, the second dielectric layer having a material different from the material of the first material layer.

Abstract: A method of manufacturing a semiconductor device is provided including providing an SOI substrate comprising a semiconductor bulk substrate, a buried insulation layer and a semiconductor layer, forming a shallow trench isolation in the SOI substrate, forming a FET in and over the SOI substrate, and forming a contact to a source or drain region of the FET that is positioned adjacent to the source or drain region, wherein forming the shallow trench isolation includes forming a trench in the SOI substrate, filling a lower portion of the trench with a first dielectric layer, forming a buffer layer over the first dielectric material layer, the buffer layer having a material different from a material of the first dielectric layer, and forming a second dielectric layer over the buffer layer and of a material different from the material of the buffer layer.

Abstract: Structures for field-effect transistors and methods for fabricating a structure for field-effect transistors. A logic cell includes first and second field-effect transistors and a well defining a back gate that is arranged beneath the first and second field-effect transistors. A dielectric layer is arranged between the well and the logic cell. A plurality of deep trench isolation regions extend through the dielectric layer and are arranged to surround the first and second field-effect transistors and the well. The back gate is shared by the first and second field-effect transistors.

Abstract: Structures for field-effect transistors and methods for fabricating a structure for field-effect transistors. A logic cell includes first and second field-effect transistors and a well defining a back gate that is arranged beneath the first and second field-effect transistors. A dielectric layer is arranged between the well and the logic cell. A plurality of deep trench isolation regions extend through the dielectric layer and are arranged to surround the first and second field-effect transistors and the well. The back gate is shared by the first and second field-effect transistors.

Abstract: A device including multiple depth STI regions with sidewall profiles, and method of production thereof Embodiments include a top region having a substantially vertical sidewall profile; and a bottom region having a width greater than or equal to the top region and a sidewall profile.

Abstract: A device including multiple depth STI regions with sidewall profiles, and method of production thereof Embodiments include a top region having a substantially vertical sidewall profile; and a bottom region having a width greater than or equal to the top region and a sidewall profile.

Abstract: In semiconductor devices, some active regions may frequently have to be formed on the basis of a silicon/germanium (Si/Ge) mixture in order to appropriately adjust transistor characteristics, for instance, for P-type transistors. To this end, the present disclosure provides manufacturing techniques and respective devices in which at least two different types of active regions, including Si/Ge material, may be provided with a high degree of compatibility with conventional process strategies. Due to the provision of different germanium concentrations, increased flexibility in adjusting characteristics of transistor elements that require Si/Ge material in their active regions may be achieved.

Abstract: In various aspects, the present disclosure relates to device structures and a method of forming such a device structure. In some illustrative embodiments herein, a device is provided, including a semiconductor substrate having a first trench formed therein, and a first trench isolation structure formed in the first trench. The first trench isolation structure includes first and second insulating liners formed adjacent inner surfaces of the first trench, wherein the first insulating liner is in direct contact with inner surfaces of the first trench and the second insulating liner is formed directly on the first insulating liner, and a first insulating filling material which at least partially fills the first trench. In some aspects, a thickness of the first insulating liner is greater than a thickness of the second insulating liner.

Abstract: One illustrative device disclosed herein is formed on an SOI substrate. The transistor device includes a first channel region formed in a semiconductor bulk substrate of the SOI substrate and a first gate insulation layer formed above the first channel region. In one embodiment, the first gate insulation layer includes a part of the buried insulation layer of the SOI substrate and an oxidized part of the semiconductor layer of the SOI substrate.

Abstract: In semiconductor devices, some active regions may frequently have to be formed on the basis of a silicon/germanium (Si/Ge) mixture in order to appropriately adjust transistor characteristics, for instance, for P-type transistors. To this end, the present disclosure provides manufacturing techniques and respective devices in which at least two different types of active regions, including Si/Ge material, may be provided with a high degree of compatibility with conventional process strategies. Due to the provision of different germanium concentrations, increased flexibility in adjusting characteristics of transistor elements that require Si/Ge material in their active regions may be achieved.