Patents by Inventor Elliot Tan
Elliot Tan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240120397Abstract: Contact over active gate (COAG) structures with conductive gate taps are described. In an example, an integrated circuit structure includes a plurality of gate structures above a substrate, each of the gate structures including a gate insulating layer thereon. Each of the plurality of gate structures includes a conductive tap structure protruding through the corresponding gate insulating layer. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a trench insulating layer thereon. An interlayer dielectric material is above the trench insulating layers and the gate insulating layers. An opening is in the interlayer dielectric material and exposes the conductive tap structure of one of the plurality of gate structures. A conductive structure is in the opening and is in direct contact with the conductive tap structure of one of the plurality of gate structures.Type: ApplicationFiled: December 18, 2023Publication date: April 11, 2024Inventor: Elliot TAN
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Publication number: 20240105596Abstract: IC devices with angled interconnects are disclosed herein. An interconnect, specifically a trench or line interconnect, is referred to as an “angled interconnect” if the interconnect is neither perpendicular nor parallel to any edges of front or back faces of the support structure, or if the interconnect is not parallel or perpendicular to interconnect in another region of an interconnect layer. Angled interconnects may be used to decrease the area of pitch transition regions. Angled interconnects may also be used to decrease the area of pitch offset regions.Type: ApplicationFiled: September 27, 2022Publication date: March 28, 2024Applicant: Intel CorporationInventors: Abhishek A. Sharma, Tahir Ghani, Wilfred Gomes, Anand S. Murthy, Shem Ogadhoh, Pushkar Sharad Ranade, Sagar Suthram, Elliot Tan
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Publication number: 20240105798Abstract: An example IC device formed using trim patterning as described herein may include a support structure, a first elongated structure (e.g., a first fin or nanoribbon) and a second elongated structure (e.g., a second fin or nanoribbon), proximate to an end of the first elongated structure. An angle between a projection of the first elongated structure on the support structure and an edge of the support structure may be between about 5 and 45 degrees, while an angle between a projection of the second elongated structure on the support structure and the edge of the support structure may be less than about 15 degrees.Type: ApplicationFiled: September 27, 2022Publication date: March 28, 2024Inventors: Abhishek A. Sharma, Tahir Ghani, Anand S. Murthy, Elliot Tan, Shem Ogadhoh, Sagar Suthram, Pushkar Sharad Ranade, Wilfred Gomes
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Publication number: 20240071955Abstract: Described herein is full wafer device that includes a computing logic formed over a substrate and two directional indicators formed in the substrate. The computing logic is arranged as a plurality of dies having a first die edge direction and a second die edge direction perpendicular to the first die edge direction. The computing logic further includes an angled feature extending in a feature direction, the feature direction different from the first die edge direction and the second die edge direction. The first directional indicator formed in the substrate indicates the first die edge direction. The second directional indicator formed in the substrate indicates the feature direction.Type: ApplicationFiled: August 31, 2022Publication date: February 29, 2024Applicant: Intel CorporationInventors: Abhishek A. Sharma, Tahir Ghani, Wilfred Gomes, Shem Ogadhoh, Swaminathan Sivakumar, Sagar Suthram, Elliot Tan
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Patent number: 11888043Abstract: Contact over active gate (COAG) structures with conductive gate taps are described. In an example, an integrated circuit structure includes a plurality of gate structures above a substrate, each of the gate structures including a gate insulating layer thereon. Each of the plurality of gate structures includes a conductive tap structure protruding through the corresponding gate insulating layer. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a trench insulating layer thereon. An interlayer dielectric material is above the trench insulating layers and the gate insulating layers. An opening is in the interlayer dielectric material and exposes the conductive tap structure of one of the plurality of gate structures. A conductive structure is in the opening and is in direct contact with the conductive tap structure of one of the plurality of gate structures.Type: GrantFiled: January 5, 2023Date of Patent: January 30, 2024Assignee: Intel CorporationInventor: Elliot Tan
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Publication number: 20230420363Abstract: IC devices with angled transistors and angled routing tracks, and related assemblies and methods, are disclosed herein. A transistor is referred to as an “angled transistor” if a longitudinal axis of an elongated semiconductor structure of the transistor (e.g., a fin or a nanoribbon) is neither perpendicular nor parallel to any edges of front or back sides of a support structure (e.g., a die) over which the transistor is implemented. Similarly, a routing track is referred to as an “angled routing track” if the routing track is neither perpendicular nor parallel to any edges of front or back faces of the support structure. Angled transistors and angled routing tracks provide a promising way to increasing densities of transistors on the limited real estate of semiconductor chips and/or decreasing adverse effects associated with continuous scaling of IC components.Type: ApplicationFiled: May 10, 2023Publication date: December 28, 2023Applicant: Intel CorporationInventors: Sagar Suthram, Elliot Tan, Abhishek A. Sharma, Shem Odhiambo Ogadhoh, Wilfred Gomes, Pushkar Sharad Ranade, Anand S. Murthy, Tahir Ghani
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Publication number: 20230422463Abstract: SRAM devices with angled transistors, and related assemblies and methods, are disclosed herein. A transistor is referred to as “angled” if a longitudinal axis of an elongated semiconductor structure (e.g., a fin or a nanoribbon) based on which the transistor is built is at an angle other than 0 degrees or 90 degrees with respect to the edges of front or back faces of a support structure or a die on/in which the transistor resides, e.g., at an angle between about 10 and 80 degrees with respect to at least one of such edges. Implementing at least some of the transistors of SRAM cells as angled transistors may provide a promising way to increasing densities of SRAM cells on the limited real estate of semiconductor chips.Type: ApplicationFiled: May 5, 2023Publication date: December 28, 2023Applicant: Intel CorporationInventors: Abhishek A. Sharma, Sagar Suthram, Kimberly L. Pierce, Elliot Tan, Pushkar Sharad Ranade, Shem Odhiambo Ogadhoh, Wilfred Gomes, Anand S. Murthy, Swaminathan Sivakumar, Tahir Ghani
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Publication number: 20230154995Abstract: Contact over active gate (COAG) structures with conductive gate taps are described. In an example, an integrated circuit structure includes a plurality of gate structures above a substrate, each of the gate structures including a gate insulating layer thereon. Each of the plurality of gate structures includes a conductive tap structure protruding through the corresponding gate insulating layer. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a trench insulating layer thereon. An interlayer dielectric material is above the trench insulating layers and the gate insulating layers. An opening is in the interlayer dielectric material and exposes the conductive tap structure of one of the plurality of gate structures. A conductive structure is in the opening and is in direct contact with the conductive tap structure of one of the plurality of gate structures.Type: ApplicationFiled: January 5, 2023Publication date: May 18, 2023Inventor: Elliot TAN
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Patent number: 11581412Abstract: Contact over active gate (COAG) structures with conductive gate taps are described. In an example, an integrated circuit structure includes a plurality of gate structures above a substrate, each of the gate structures including a gate insulating layer thereon. Each of the plurality of gate structures includes a conductive tap structure protruding through the corresponding gate insulating layer. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a trench insulating layer thereon. An interlayer dielectric material is above the trench insulating layers and the gate insulating layers. An opening is in the interlayer dielectric material and exposes the conductive tap structure of one of the plurality of gate structures. A conductive structure is in the opening and is in direct contact with the conductive tap structure of one of the plurality of gate structures.Type: GrantFiled: January 2, 2019Date of Patent: February 14, 2023Assignee: Intel CorporationInventor: Elliot Tan
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Publication number: 20220189957Abstract: Disclosed herein are transistors, memory cells, and arrangements thereof. For example, in some embodiments, an integrated circuit (IC) structure may include a plurality of transistors, wherein the transistors are distributed in a hexagonally packed arrangement. In another example, in some embodiments, an IC structure may include a memory cell including an axially symmetric transistor coupled to an axially symmetric capacitor, wherein the axis of the transistor is aligned with the axis of the capacitor.Type: ApplicationFiled: December 10, 2020Publication date: June 16, 2022Applicant: Intel CorporationInventors: Sarah Atanasov, Abhishek A. Sharma, Bernhard Sell, Chieh-Jen Ku, Elliot Tan, Hui Jae Yoo, Noriyuki Sato, Travis W. Lajoie, Van H. Le
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Publication number: 20220189913Abstract: Disclosed herein are transistors, memory cells, and arrangements thereof. For example, in some embodiments, an integrated circuit (IC) structure may include a plurality of transistors, wherein the transistors are distributed in a hexagonally packed arrangement. In another example, in some embodiments, an IC structure may include a memory cell including an axially symmetric transistor coupled to an axially symmetric capacitor, wherein the axis of the transistor is aligned with the axis of the capacitor.Type: ApplicationFiled: December 10, 2020Publication date: June 16, 2022Applicant: Intel CorporationInventors: Sarah Atanasov, Abhishek A. Sharma, Bernhard Sell, Chieh-Jen Ku, Elliot Tan, Hui Jae Yoo, Noriyuki Sato, Travis W. Lajoie, Van H. Le, Thoe Michaelos
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Patent number: 11189614Abstract: A grating structure has a plurality of grating members that extend upward from a base in a spaced-apart parallel relationship and include an end member. For example, the grating structure is a plurality of semiconductor fins on a base. The base can be any structure underlying the grating members. The grating members have a member width and a member height. Adjacent grating members are spaced by a grating spacing. A process artifact is adjacent the end member and is spaced from the end member by a horizontal distance consistent with the member spacing. In some cases, the process artifact can be a stub of a second material on or otherwise extending from the base adjacent an end member of the grating structure. In other cases, the process artifact can be a recess in or otherwise extending into the base adjacent an end member of the grating structure.Type: GrantFiled: March 16, 2018Date of Patent: November 30, 2021Assignee: Intel CorporationInventors: Leonard Guler, Elliot Tan
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Publication number: 20210335791Abstract: A three-dimensional memory array may include a first memory array and a second memory array, stacked above the first. Some memory cells of the first array may be coupled to a first layer selector transistor, while some memory cells of the second array may be coupled to a second layer selector transistor. The first and second layer selector transistor may be coupled to one another and to a peripheral circuit that controls operation of the first and/or second memory arrays. A different layer selector transistor may be used for each row of memory cells of a given memory array and/or for each column of memory cells of a given memory array. Such designs may allow increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density.Type: ApplicationFiled: July 6, 2021Publication date: October 28, 2021Applicant: Intel CorporationInventors: Wilfred Gomes, Mauro J. Kobrinsky, Abhishek A. Sharma, Rajesh Kumar, Kinyip Phoa, Elliot Tan, Tahir Ghani, Swaminathan Sivakumar
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Patent number: 11139300Abstract: A three-dimensional memory array may include a first memory array and a second memory array, stacked above the first. Some memory cells of the first array may be coupled to a first layer selector transistor, while some memory cells of the second array may be coupled to a second layer selector transistor. The first and second layer selector transistor may be coupled to one another and to a peripheral circuit that controls operation of the first and/or second memory arrays. A different layer selector transistor may be used for each row of memory cells of a given memory array and/or for each column of memory cells of a given memory array. Such designs may allow increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density.Type: GrantFiled: November 20, 2019Date of Patent: October 5, 2021Assignee: Intel CorporationInventors: Wilfred Gomes, Mauro J. Kobrinsky, Abhishek A. Sharma, Rajesh Kumar, Kinyip Phoa, Elliot Tan, Tahir Ghani, Swaminathan Sivakumar
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Patent number: 11056492Abstract: Described herein are memory arrays where some memory cells include access transistors with one front-side and one back-side source/drain (S/D) contacts. An example memory array further includes a bitline, coupled to the first S/D region of the access transistor of a first memory cell of the memory array, and a plateline, coupled to a first capacitor electrode of a storage capacitor of the first memory cell. Because the access transistor is a transistor with one front-side and one back-side S/D contacts, the bitline may be provided in a first layer, the channel material—in a second layer, and the plateline—in a third layer, where the second layer is between the first layer and the third layer, which may allow increasing the density of memory cells in a memory array, or, conversely, reducing the footprint area of a memory array with a given density of memory cells.Type: GrantFiled: December 23, 2019Date of Patent: July 6, 2021Assignee: Intel CorporationInventors: Wilfred Gomes, Mauro J. Kobrinsky, Elliot Tan, Szuya S. Liao, Tahir Ghani, Swaminathan Sivakumar, Rajesh Kumar
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Patent number: 11056397Abstract: Disclosed herein are techniques for directional spacer removal, as well as related integrated circuit (IC) structures and devices. For example, in some embodiments, an IC structure may include: a first semiconductor fin having a first fin end cap; a second semiconductor fin having a second fin end cap, wherein the second fin end cap faces the first fin end cap; a first gate over the first semiconductor fin, wherein the first gate has a first gate end cap; a second gate over the second semiconductor fin, wherein the second gate has a second gate end cap facing the first gate end cap; and a gate edge isolation material adjacent to the first fin end cap, the second fin end cap, the first gate end cap, and the second gate end cap.Type: GrantFiled: September 26, 2017Date of Patent: July 6, 2021Assignee: Intel CorporationInventors: Leonard P. Guler, Elliot Tan
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Publication number: 20210193666Abstract: Described herein are memory arrays where some memory cells include access transistors with one front-side and one back-side source/drain (S/D) contacts. An example memory array further includes a bitline, coupled to the first S/D region of the access transistor of a first memory cell of the memory array, and a plateline, coupled to a first capacitor electrode of a storage capacitor of the first memory cell. Because the access transistor is a transistor with one front-side and one back-side S/D contacts, the bitline may be provided in a first layer, the channel material—in a second layer, and the plateline—in a third layer, where the second layer is between the first layer and the third layer, which may allow increasing the density of memory cells in a memory array, or, conversely, reducing the footprint area of a memory array with a given density of memory cells.Type: ApplicationFiled: December 23, 2019Publication date: June 24, 2021Applicant: Intel CorporationInventors: Wilfred Gomes, Mauro J. Kobrinsky, Elliot Tan, Szuya S. Liao, Tahir Ghani, Swaminathan Sivakumar, Rajesh Kumar
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Publication number: 20210151438Abstract: A three-dimensional memory array may include a first memory array and a second memory array, stacked above the first. Some memory cells of the first array may be coupled to a first layer selector transistor, while some memory cells of the second array may be coupled to a second layer selector transistor. The first and second layer selector transistor may be coupled to one another and to a peripheral circuit that controls operation of the first and/or second memory arrays. A different layer selector transistor may be used for each row of memory cells of a given memory array and/or for each column of memory cells of a given memory array. Such designs may allow increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density.Type: ApplicationFiled: November 20, 2019Publication date: May 20, 2021Applicant: Intel CorporationInventors: Wilfred Gomes, Mauro J. Kobrinsky, Abhishek A. Sharma, Rajesh Kumar, Kinyip Phoa, Elliot Tan, Tahir Ghani, Swaminathan Sivakumar
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Publication number: 20200373205Abstract: Disclosed herein are techniques for directional spacer removal, as well as related integrated circuit (IC) structures and devices. For example, in some embodiments, an IC structure may include: a first semiconductor fin having a first fin end cap; a second semiconductor fin having a second fin end cap, wherein the second fin end cap faces the first fin end cap; a first gate over the first semiconductor fin, wherein the first gate has a first gate end cap; a second gate over the second semiconductor fin, wherein the second gate has a second gate end cap facing the first gate end cap; and a gate edge isolation material adjacent to the first fin end cap, the second fin end cap, the first gate end cap, and the second gate end cap.Type: ApplicationFiled: September 26, 2017Publication date: November 26, 2020Applicant: Intel CorporationInventors: Leonard P. Guler, Elliot Tan
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Publication number: 20200212189Abstract: Contact over active gate (COAG) structures with conductive gate taps are described. In an example, an integrated circuit structure includes a plurality of gate structures above a substrate, each of the gate structures including a gate insulating layer thereon. Each of the plurality of gate structures includes a conductive tap structure protruding through the corresponding gate insulating layer. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a trench insulating layer thereon. An interlayer dielectric material is above the trench insulating layers and the gate insulating layers. An opening is in the interlayer dielectric material and exposes the conductive tap structure of one of the plurality of gate structures. A conductive structure is in the opening and is in direct contact with the conductive tap structure of one of the plurality of gate structures.Type: ApplicationFiled: January 2, 2019Publication date: July 2, 2020Inventor: Elliot TAN