Patents by Inventor Elliott C. Cooper-Balis

Elliott C. Cooper-Balis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11893279
    Abstract: An access tracker configured to receive a request to access a page, determine whether a page identification (ID) associated with the page is in the access tracker, increment an access count of the page in response to determining the page ID is in the access tracker, sort a number of page IDs based on an access count of each page ID, and determine whether a different page is hot or cold in response to sorting the number of page IDs.
    Type: Grant
    Filed: August 25, 2021
    Date of Patent: February 6, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Cagdas Dirik, Robert M. Walker, Elliott C. Cooper-Balis
  • Publication number: 20240036762
    Abstract: Systems, apparatuses, and methods related to bloom filter implementation into a controller are described. A memory device is coupled to a memory controller. The memory controller is configured to implement a counting bloom filter, increment the counting bloom filter in response to a row activate command of the memory device, determine whether a value of the counting bloom filter exceeds a threshold value, and perform an action in response to the value exceeding the threshold value.
    Type: Application
    Filed: July 27, 2023
    Publication date: February 1, 2024
    Inventors: Edmund J. Gieske, Cagdas Dirik, Elliott C. Cooper-Balis, Robert M. Walker, Amitava Majumdar, Sujeet Ayyapureddi, Yang Lu, Ameen D. Akel, Niccolò Izzo, Danilo Caraccio, Markus H. Geiger
  • Publication number: 20230393770
    Abstract: Systems, methods, and apparatus for memory device security and row hammer mitigation are described. A control mechanism may be implemented in a front-end and/or a back-end of a memory sub-system to refresh rows of the memory. A row activation command having a row address at control circuitry of a memory sub-system and incrementing a first count of a row counter corresponding to the row address stored in a content addressable memory (CAM) of the memory sub-system may be received. Control circuitry may determine whether the first count is greater than a row hammer threshold (RHT) minus a second count of a CAM decrease counter (CDC); the second count may be incremented each time the CAM is full. A refresh command to the row address may be issued when a determination is made that the first count is greater than the RHT minus the second count.
    Type: Application
    Filed: September 16, 2022
    Publication date: December 7, 2023
    Inventors: Yang Lu, Sujeet Ayyapureddi, Edmund J. Gieske, Cagdas Dirik, Ameen D. Akel, Elliott C. Cooper-Balis, Amitava Majumdar, Robert M. Walker, Danilo Caraccio
  • Patent number: 11755515
    Abstract: Systems and techniques for a translation device that is configured to enable communication between a host device and a memory technology using different communication protocols (e.g., a communication protocol that is not preconfigured in the host device) is described herein. The translation device may be configured to receive signals from the host device using a first communication protocol and transmit signals to the memory device using a second communication protocol, or vice-versa. When converting signals between different communication protocols, the translation device may be configured to convert commands, map memory addresses to new addresses, map between channels having different characteristics, encode data using different modulation schemes, or a combination thereof.
    Type: Grant
    Filed: March 2, 2022
    Date of Patent: September 12, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Brent Keeth, Richard C. Murphy, Elliott C. Cooper-Balis
  • Publication number: 20230282258
    Abstract: Systems and methods for finite time counting period counting of infinite data streams is presented. In particular example systems and methods enable counting row accesses to a memory media device over predetermined time intervals in order to deterministically detect row hammer attacks on the memory media device. Example embodiments use two identical tables that are reset at times offset in relation to each other in a ping-pong manner in order to ensure that there exists no false negative detections. The counting techniques described in this disclosure can be used in various types of row hammer mitigation techniques and can be implemented in content addressable memory or another type of memory. The mitigation may be implemented on a per-bank basis, per-channel basis or per-memory media device basis. The memory media device may be a dynamic random access memory type device.
    Type: Application
    Filed: January 26, 2023
    Publication date: September 7, 2023
    Applicant: Micron Technology, Inc.
    Inventors: Edmund GIESKE, Amitava MAJUMDAR, Cagdas DIRIK, Sujeet AYYAPUREDDI, Yang LU, Ameen D. AKEL, Danilo CARACCIO, Niccolo' IZZO, Elliott C. COOPER-BALIS, Markus H. GEIGER
  • Publication number: 20230238046
    Abstract: An energy-efficient and area-efficient, mitigation of errors in a memory media device that are caused by row hammer attacks and the like is described. The detection of errors is deterministically performed while maintaining, in an SRAM, a number of row access counters that is smaller than the total number of rows protected in the memory media device. The reduction of the number of required counters is achieved by aliasing a plurality of rows that are being protected to each counter. The mitigation may be implemented on a per-bank basis, per-channel basis or per-memory media device basis. The memory media device may be DRAM.
    Type: Application
    Filed: September 9, 2022
    Publication date: July 27, 2023
    Applicant: Micron Technology, Inc.
    Inventors: Edmund GIESKE, Cagdas DIRIK, Robert M. WALKER, Sujeet AYYAPUREDDI, Niccolo IZZO, Markus GEIGER, Yang LU, Ameen AKEL, Elliott C. COOPER-BALIS, Danilo CARACCIO
  • Publication number: 20230236735
    Abstract: Systems and methods for area-efficient mitigation of errors that are caused by row hammer attacks and the like in a memory media device are described. The counters for counting row accesses are maintained in a content addressable memory (CAM) the provides fast access times. The detection of errors is deterministically performed while maintaining a number of row access counters that is smaller than the total number of rows protected in the memory media device. The circuitry for the detection and mitigation may be in the memory media device or in a memory controller to which the memory media device attaches. The memory media device may be dynamic random access memory (DRAM).
    Type: Application
    Filed: August 29, 2022
    Publication date: July 27, 2023
    Applicant: Micron Technology, Inc.
    Inventors: Sujeet AYYAPUREDDI, Yang LU, Edmund GIESKE, Cagdas DIRIK, Ameen D. AKEL, Elliott C. COOPER-BALIS, Amitava MAJUMDAR, Danilo CARACCIO, Robert M. WALKER
  • Publication number: 20230064745
    Abstract: An access tracker configured to receive a request to access a page, determine whether a page identification (ID) associated with the page is in the access tracker, increment an access count of the page in response to determining the page ID is in the access tracker, sort a number of page IDs based on an access count of each page ID, and determine whether a different page is hot or cold in response to sorting the number of page IDs.
    Type: Application
    Filed: August 25, 2021
    Publication date: March 2, 2023
    Inventors: Cagdas Dirik, Robert M. Walker, Elliott C. Cooper-Balis
  • Publication number: 20230041486
    Abstract: An apparatus can include a memory device comprising a memory component and a memory controller that is coupled to the memory component. A memory searching component (MSC) is resident on the apparatus. The MSC can receive an external instruction indicative of performance of an operation to retrieve particular data from the memory component and issue, responsive to receipt of the instruction, a command to the memory controller to cause the memory controller to perform a read request invoking the memory component as part of performance of the operation in the absence of a further external instruction.
    Type: Application
    Filed: October 24, 2022
    Publication date: February 9, 2023
    Inventors: Elliott C. Cooper-Balis, Robert M. Walker, Paul Rosenfeld
  • Patent number: 11494119
    Abstract: An apparatus can include a memory device comprising a memory component and a memory controller that is coupled to the memory component. A memory searching component (MSC) is resident on the apparatus. The MSC can receive an external instruction indicative of performance of an operation to retrieve particular data from the memory component and issue, responsive to receipt of the instruction, a command to the memory controller to cause the memory controller to perform a read request invoking the memory component as part of performance of the operation in the absence of a further external instruction.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: November 8, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Elliott C. Cooper-Balis, Robert M. Walker, Paul Rosenfeld
  • Publication number: 20220188253
    Abstract: Systems and techniques for a translation device that is configured to enable communication between a host device and a memory technology using different communication protocols (e.g., a communication protocol that is not preconfigured in the host device) is described herein. The translation device may be configured to receive signals from the host device using a first communication protocol and transmit signals to the memory device using a second communication protocol, or vice-versa. When converting signals between different communication protocols, the translation device may be configured to convert commands, map memory addresses to new addresses, map between channels having different characteristics, encode data using different modulation schemes, or a combination thereof.
    Type: Application
    Filed: March 2, 2022
    Publication date: June 16, 2022
    Inventors: Brent Keeth, Richard C. Murphy, Elliott C. Cooper-Balis
  • Patent number: 11281608
    Abstract: Systems and techniques for a translation device that is configured to enable communication between a host device and a memory technology using different communication protocols (e.g., a communication protocol that is not preconfigured in the host device) is described herein. The translation device may be configured to receive signals from the host device using a first communication protocol and transmit signals to the memory device using a second communication protocol, or vice-versa. When converting signals between different communication protocols, the translation device may be configured to convert commands, map memory addresses to new addresses, map between channels having different characteristics, encode data using different modulation schemes, or a combination thereof.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: March 22, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Brent Keeth, Richard C. Murphy, Elliott C. Cooper-Balis
  • Publication number: 20220075558
    Abstract: An apparatus can include a memory device comprising a memory component and a memory controller that is coupled to the memory component. A memory searching component (MSC) is resident on the apparatus. The MSC can receive an external instruction indicative of performance of an operation to retrieve particular data from the memory component and issue, responsive to receipt of the instruction, a command to the memory controller to cause the memory controller to perform a read request invoking the memory component as part of performance of the operation in the absence of a further external instruction.
    Type: Application
    Filed: September 10, 2020
    Publication date: March 10, 2022
    Inventors: Elliott C. Cooper-Balis, Robert M. Walker, Paul Rosenfeld
  • Patent number: 10838897
    Abstract: Systems and techniques for a translation device that is configured to enable communication between a host device and a memory technology using different communication protocols (e.g., a communication protocol that is not preconfigured in the host device) is described herein. The translation device may be configured to receive signals from the host device using a first communication protocol and transmit signals to the memory device using a second communication protocol, or vice-versa. When converting signals between different communication protocols, the translation device may be configured to convert commands, map memory addresses to new addresses, map between channels having different characteristics, encode data using different modulation schemes, or a combination thereof.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: November 17, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Brent Keeth, Richard C. Murphy, Elliott C. Cooper-Balis
  • Publication number: 20200210361
    Abstract: Systems and techniques for a translation device that is configured to enable communication between a host device and a memory technology using different communication protocols (e.g., a communication protocol that is not preconfigured in the host device) is described herein. The translation device may be configured to receive signals from the host device using a first communication protocol and transmit signals to the memory device using a second communication protocol, or vice-versa. When converting signals between different communication protocols, the translation device may be configured to convert commands, map memory addresses to new addresses, map between channels having different characteristics, encode data using different modulation schemes, or a combination thereof.
    Type: Application
    Filed: March 11, 2020
    Publication date: July 2, 2020
    Inventors: Brent Keeth, Richard C. Murphy, Elliott C. Cooper-Balis
  • Patent number: 10628354
    Abstract: Systems and techniques for a translation device that is configured to enable communication between a host device and a memory technology using different communication protocols (e.g., a communication protocol that is not preconfigured in the host device) is described herein. The translation device may be configured to receive signals from the host device using a first communication protocol and transmit signals to the memory device using a second communication protocol, or vice-versa. When converting signals between different communication protocols, the translation device may be configured to convert commands, map memory addresses to new addresses, map between channels having different characteristics, encode data using different modulation schemes, or a combination thereof.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: April 21, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Brent Keeth, Richard C. Murphy, Elliott C. Cooper-Balis
  • Publication number: 20190179785
    Abstract: Systems and techniques for a translation device that is configured to enable communication between a host device and a memory technology using different communication protocols (e.g., a communication protocol that is not preconfigured in the host device) is described herein. The translation device may be configured to receive signals from the host device using a first communication protocol and transmit signals to the memory device using a second communication protocol, or vice-versa. When converting signals between different communication protocols, the translation device may be configured to convert commands, map memory addresses to new addresses, map between channels having different characteristics, encode data using different modulation schemes, or a combination thereof.
    Type: Application
    Filed: August 8, 2018
    Publication date: June 13, 2019
    Inventors: Brent Keeth, Richard C. Murphy, Elliott C. Cooper-Balis
  • Publication number: 20190179769
    Abstract: Systems and techniques for a translation device that is configured to enable communication between a host device and a memory technology using different communication protocols (e.g., a communication protocol that is not preconfigured in the host device) is described herein. The translation device may be configured to receive signals from the host device using a first communication protocol and transmit signals to the memory device using a second communication protocol, or vice-versa. When converting signals between different communication protocols, the translation device may be configured to convert commands, map memory addresses to new addresses, map between channels having different characteristics, encode data using different modulation schemes, or a combination thereof.
    Type: Application
    Filed: August 8, 2018
    Publication date: June 13, 2019
    Inventors: Brent Keeth, Richard C. Murphy, Elliott C. Cooper-Balis