Abstract: An apparatus having a first interface for coupling to a first component bus; a second interface for coupling to a second component bus; an address translation unit coupled to the second interface; and a bus bridge coupled to the first interface and to the second interface.

Abstract: A processor for creating an intelligent input/output subsystems which includes a local processor coupled to a local system bus; a local memory controller coupled to the local system bus that enables access to a memory from the local system bus; a bus bridge having a first bus interface coupled to a first component bus; a second bus interface coupled to a second component bus, the bus bridge including means for creating an address space which is private to the secondary component bus such that the bridge will not send any address found in the private address space upstream to the primary component bus; and address translation means coupled to the local system bus and the bus bridge for translating addresses between the local system bus and the second component bus.