Abstract: A semiconductor package includes a lead structure upon which a semiconductor die is mounted with at least some portion of at least some of the leads extending to, at, or across an axis or axis of the package to militate against thermally induced growth of the package and the reduce or minimize strain within the package and reliability issue associated therewith.

Abstract: A semiconductor package includes a lead structure upon which a semiconductor die is mounted with at least some portion of at least some of the leads extending to, at, or across an axis or axis of the package to militate against thermally induced growth of the package and the reduce or minimize strain within the package and reliability issuse associated therewith.

Abstract: A microelectronic assembly and a fabrication method are provided which includes a microelectronic element such as a chip or element of a package. A plurality of surface-mountable contacts are arranged in an array exposed at a major surface of the microelectronic element. One or more passive elements, e.g., a resistor, inductor, capacitor, or combination of the same are mounted to the microelectronic element, with an inner terminal of the passive element conductively mounted to an exposed surface of one contact and an outer terminal displaced vertically from the major surface of the microelectronic element.

Abstract: A semiconductor package includes a lead structure upon which a semiconductor die is mounted with at least some portion of at least some of the leads extending to, at, or across an axis or axis of the package to militate against thermally induced growth of the package and the reduce or minimize strain within the package and reliability issuse associated therewith.

Abstract: A stacked chip assembly includes individual units having chips mounted on dielectric layers and traces on the dielectric layers interconnecting the contacts of the chips with terminals disposed in peripheral regions of the dielectric layers. At least some of the traces are multi-branched traces which connect chip select contacts to chip select terminals. The units are stacked one above the other with corresponding terminals of the different units being connected to one another by solder balls or other conductive elements so as to form vertical buses. Prior to stacking, the multi-branched traces of the individual units are selectively connected, as by forming solder bridges, so as to leave chip select contacts of chips in different units connected to different chip select terminals and thereby connect these chips to different vertical buses. The individual units desirably are thin and directly abut one another so as to provide a low-height assembly with good heat transfer from chips within the stack.

Abstract: A stacked chip assembly includes individual units having chips mounted on dielectric layers and traces on the dielectric layers interconnecting the contacts of the chips with terminals disposed in peripheral regions of the dielectric layers. At least some of the traces are multi-branched traces which connect chip select contacts to chip select terminals. The units are stacked one above the other with corresponding terminals of the different units being connected to one another by solder balls or other conductive elements so as to form vertical buses. Prior to stacking, the multi-branched traces of the individual units are selectively interrupted, as by breaking the individual branches, so as to leave chip select contacts of chips in different units connected to different chip select terminals and thereby connect these chips to different vertical buses.

Abstract: A stacked chip assembly includes individual units having chips mounted on dielectric layers and traces on the dielectric layers interconnecting the contacts of the chips with terminals disposed in peripheral regions of the dielectric layers. At least some of the traces are multi-branched traces which connect chip select contacts to chip select terminals. The units are stacked one above the other with corresponding terminals of the different units being connected to one another by solder balls or other conductive elements so as to form vertical buses. Prior to stacking, the multi-branched traces of the individual units are selectively interrupted, as by breaking the individual branches, so as to leave chip select contacts of chips in different units connected to different chip select terminals and thereby connect these chips to different vertical buses.

Abstract: A stacked chip assembly includes individual units having chips mounted on dielectric layers and traces on the dielectric layers interconnecting the contacts of the chips with terminals disposed in peripheral regions of the dielectric layers. At least some of the traces are multi-branched traces which connect chip select contacts to chip select terminals. The units are stacked one above the other with corresponding terminals of the different units being connected to one another by solder balls or other conductive elements so as to form vertical buses. Prior to stacking, the multi-branched traces of the individual units are selectively interrupted, as by breaking the individual branches, so as to leave chip select contacts of chips in different units connected to different chip select terminals and thereby connect these chips to different vertical buses.

Abstract: A method of making a microelectronic assembly comprises providing a first side assembly juxtaposed with a second side assembly and a first resilient element disposed therebetween. Leads extend between the first side assembly and the second side assembly. A compressive force is applied to the juxtaposed assemblies so as to compress the first resilient element and the compressive force is at least partially released so as to allow the first resilient element to expand, thereby moving one or both of the first side assembly and the second side assembly to deform the leads.

Abstract: A stacked chip assembly includes individual units having chips mounted on dielectric layers and traces on the dielectric layers interconnecting the contacts of the chips with terminals disposed in peripheral regions of the dielectric layers. At least some of the traces are multi-branched traces which connect chip select contacts to chip select terminals. The units are stacked one above the other with corresponding terminals of the different units being connected to one another by solder balls or other conductive elements so as to form vertical buses. Prior to stacking, the multi-branched traces of the individual units are selectively connected, as by forming solder bridges, so as to leave chip select contacts of chips in different units connected to different chip select terminals and thereby connect these chips to different vertical buses. The individual units desirably are thin and directly abut one another so as to provide a low-height assembly with good heat transfer from chips within the stack.

Abstract: A stacked chip assembly includes individual units having chips mounted on dielectric layers and traces on the dielectric layers interconnecting the contacts of the chips with terminals disposed in peripheral regions of the dielectric layers. At least some of the traces are multi-branched traces which connect chip select contacts to chip select terminals. The units are stacked one above the other with corresponding terminals of the different units being connected to one another by solder balls or other conductive elements so as to form vertical buses. Prior to stacking, the multi-branched traces of the individual units are selectively interrupted, as by breaking the individual branches, so as to leave chip select contacts of chips in different units connected to different chip select terminals and thereby connect these chips to different vertical buses.

Abstract: A method of making a microelectronic assembly comprises providing a first side assembly juxtaposed with a second side assembly and a first resilient element disposed therebetween. Leads extend between the first side assembly and the second side assembly. A compressive force is applied to the juxtaposed assemblies so as to compress the first resilient element and the compressive force is at least partially released so as to allow the first resilient element to expand, thereby moving one or both of the first side assembly and the second side assembly to deform the leads.