Patents by Inventor Ellis Chang
Ellis Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220230293Abstract: Mixed-mode includes receiving inspection results including one or more images of a selected region of the wafer, the one or more images include one or more wafer die including a set of repeating blocks, the set of repeating blocks a set of repeating cells. In addition, mixed-mode inspection includes adjusting a pixel size of the one or more images to map each cell, block and die to an integer number of pixels. Further, mixed-mode inspection includes comparing a first wafer die to a second wafer die to identify an occurrence of one or more defects in the first or second wafer die, comparing a first block to a second block to identify an occurrence of one or more defects in the first or second blocks and comparing a first cell to a second cell to identify an occurrence of one or more defects in the first or second cells.Type: ApplicationFiled: April 4, 2022Publication date: July 21, 2022Inventors: Jason Z. Lin, Allen Park, Ellis Chang, Richard Wallingford, Songnian Rong, Chetana Bhaskar
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Patent number: 11348222Abstract: Methods and systems for inspection of wafers and reticles using designer intent data are provided. One computer-implemented method includes identifying nuisance defects on a wafer based on inspection data produced by inspection of a reticle, which is used to form a pattern on the wafer prior to inspection of the wafer. Another computer-implemented method includes detecting defects on a wafer by analyzing data generated by inspection of the water in combination with data representative of a reticle, which includes designations identifying different types of portions of the reticle. An additional computer-implemented method includes determining a property of a manufacturing process used to process a wafer based on defects that alter a characteristic of a device formed on the wafer. Further computer-implemented methods include altering or simulating one or more characteristics of a design of an integrated circuit based on data generated by inspection of a wafer.Type: GrantFiled: November 7, 2019Date of Patent: May 31, 2022Assignee: KLA-Tencor Technologies Corp.Inventors: Paul Frank Marella, Sharon McCauley, Ellis Chang, William Volk, James Wiley, Sterling Watson, Sagar A. Kekare, Carl Hess
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Patent number: 11295438Abstract: Mixed-mode includes receiving inspection results including one or more images of a selected region of the wafer, the one or more images include one or more wafer die including a set of repeating blocks, the set of repeating blocks a set of repeating cells. In addition, mixed-mode inspection includes adjusting a pixel size of the one or more images to map each cell, block and die to an integer number of pixels. Further, mixed-mode inspection includes comparing a first wafer die to a second wafer die to identify an occurrence of one or more defects in the first or second wafer die, comparing a first block to a second block to identify an occurrence of one or more defects in the first or second blocks and comparing a first cell to a second cell to identify an occurrence of one or more defects in the first or second cells.Type: GrantFiled: November 30, 2018Date of Patent: April 5, 2022Assignee: KLA CorporationInventors: Jason Z. Lin, Allen Park, Ellis Chang, Richard Wallingford, Songnian Rong, Chetana Bhaskar
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Patent number: 10713771Abstract: Methods and systems for inspection of wafers and reticles using designer intent data are provided. One computer-implemented method includes identifying nuisance defects on a wafer based on inspection data produced by inspection of a reticle, which is used to form a pattern on the wafer prior to inspection of the wafer. Another computer-implemented method includes detecting defects on a wafer by analyzing data generated by inspection of the wafer in combination with data representative of a reticle, which includes designations identifying different types of portions of the reticle. An additional computer-implemented method includes determining a property of a manufacturing process used to process a wafer based on defects that alter a characteristic of a device formed on the wafer. Further computer-implemented methods include altering or simulating one or more characteristics of a design of an integrated circuit based on data generated by inspection of a wafer.Type: GrantFiled: April 25, 2018Date of Patent: July 14, 2020Assignee: KLA-Tencor Technologies Corp.Inventors: Paul Frank Marella, Sharon McCauley, Ellis Chang, William Volk, James Wiley, Sterling Watson, Sagar A. Kekare, Carl Hess
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Publication number: 20200074619Abstract: Methods and systems for inspection of wafers and reticles using designer intent data are provided. One computer-implemented method includes identifying nuisance defects on a wafer based on inspection data produced by inspection of a reticle, which is used to form a pattern on the wafer prior to inspection of the wafer. Another computer-implemented method includes detecting defects on a wafer by analyzing data generated by inspection of the water in combination with data representative of a reticle, which includes designations identifying different types of portions of the reticle. An additional computer-implemented method includes determining a property of a manufacturing process used to process a wafer based on defects that alter a characteristic of a device formed on the wafer. Further computer-implemented methods include altering or simulating one or more characteristics of a design of an integrated circuit based on data generated by inspection of a wafer.Type: ApplicationFiled: November 7, 2019Publication date: March 5, 2020Inventors: Paul Frank Marella, Sharon McCauley, Ellis Chang, William Volk, James Wiley, Sterling Watson, Sagar A. Kekare, Carl Hess
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Patent number: 10387608Abstract: A semiconductor fabrication system includes a target design device and a multi-stage fabrication tool configured to fabricate one or more layers of a sample using the fabrication process. The target design device receives metrology design rules associated with a metrology tool in which the metrology design rules include criteria for one or more physical attributes of metrology targets measurable with the metrology tool. The target design device may further receive process design rules associated with a fabrication process in which the process design rules include criteria for determining process stages of the fabrication process required to fabricate structures with selected physical attributes.Type: GrantFiled: October 6, 2017Date of Patent: August 20, 2019Assignee: KLA-Tencor CorporationInventors: Michael Adel, Tal Shusterman, Chen Dror, Ellis Chang
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Publication number: 20190108630Abstract: Mixed-mode includes receiving inspection results including one or more images of a selected region of the wafer, the one or more images include one or more wafer die including a set of repeating blocks, the set of repeating blocks a set of repeating cells. In addition, mixed-mode inspection includes adjusting a pixel size of the one or more images to map each cell, block and die to an integer number of pixels. Further, mixed-mode inspection includes comparing a first wafer die to a second wafer die to identify an occurrence of one or more defects in the first or second wafer die, comparing a first block to a second block to identify an occurrence of one or more defects in the first or second blocks and comparing a first cell to a second cell to identify an occurrence of one or more defects in the first or second cells.Type: ApplicationFiled: November 30, 2018Publication date: April 11, 2019Inventors: Jason Z. Lin, Allen Park, Ellis Chang, Richard Wallingford, Songnian Rong, Chetana Bhaskar
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Patent number: 10192303Abstract: Mixed-mode includes receiving inspection results including one or more images of a selected region of the wafer, the one or more images include one or more wafer die including a set of repeating blocks, the set of repeating blocks a set of repeating cells. In addition, mixed-mode inspection includes adjusting a pixel size of the one or more images to map each cell, block and die to an integer number of pixels. Further, mixed-mode inspection includes comparing a first wafer die to a second wafer die to identify an occurrence of one or more defects in the first or second wafer die, comparing a first block to a second block to identify an occurrence of one or more defects in the first or second blocks and comparing a first cell to a second cell to identify an occurrence of one or more defects in the first or second cells.Type: GrantFiled: November 11, 2013Date of Patent: January 29, 2019Assignee: KLA Tencor CorporationInventors: Jason Z. Lin, Allen Park, Ellis Chang, Richard Wallingford, Songnian Rong, Chetana Bhaskar
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Publication number: 20180247403Abstract: Methods and systems for inspection of wafers and reticles using designer intent data are provided. One computer-implemented method includes identifying nuisance defects on a wafer based on inspection data produced by inspection of a reticle, which is used to form a pattern on the wafer prior to inspection of the wafer. Another computer-implemented method includes detecting defects on a wafer by analyzing data generated by inspection of the wafer in combination with data representative of a reticle, which includes designations identifying different types of portions of the reticle. An additional computer-implemented method includes determining a property of a manufacturing process used to process a wafer based on defects that alter a characteristic of a device formed on the wafer. Further computer-implemented methods include altering or simulating one or more characteristics of a design of an integrated circuit based on data generated by inspection of a wafer.Type: ApplicationFiled: April 25, 2018Publication date: August 30, 2018Inventors: Paul Frank Marella, Sharon McCauley, Ellis Chang, William Volk, James Wiley, Sterling Watson, Sagar A. Kekare, Carl Hess
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Patent number: 9910953Abstract: A metrology design and verification framework is provided, which includes methods and systems for metrology structure identification in an integrated circuit design data block, design rule checking, hierarchal design of metrology target structures to minimize random errors, and metrology design rule verification of metrology target design files. In-die metrology targets are identified using various filtering methods and/or designed as hierarchical structure within dies or outside the dies. Particularly, metrology target design files are generated, which are hierarchical in structure and compatible with design rule checks. Design rule check takes into account the hierarchical and often repetitive target designs in the verification process. Layouts may be verified using design rule checks at different levels of design rules, which may be combined to remove rule violations and errors prior to actual target production.Type: GrantFiled: March 4, 2014Date of Patent: March 6, 2018Assignee: KLA-Tencor CorporationInventors: Michael Adel, Tal Shusterman, Chen Dror, Ellis Chang
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Publication number: 20180032662Abstract: A semiconductor fabrication system includes a target design device and a multi-stage fabrication tool configured to fabricate one or more layers of a sample using the fabrication process. The target design device receives metrology design rules associated with a metrology tool in which the metrology design rules include criteria for one or more physical attributes of metrology targets measurable with the metrology tool. The target design device may further receive process design rules associated with a fabrication process in which the process design rules include criteria for determining process stages of the fabrication process required to fabricate structures with selected physical attributes.Type: ApplicationFiled: October 6, 2017Publication date: February 1, 2018Inventors: Michael Adel, Tal Shusterman, Chen Dror, Ellis Chang
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Publication number: 20170161418Abstract: Various embodiments for using three-dimensional representations for defect-related applications are provided. One computer-implemented method for determining one or more inspection parameters for a wafer inspection recipe includes generating a three-dimensional representation of one or more layers of a wafer based on design data. The method also includes determining one or more inspection parameters for a wafer inspection recipe based on the three-dimensional representation.Type: ApplicationFiled: February 20, 2017Publication date: June 8, 2017Inventors: Allen Park, Ellis Chang, Prashant A. Aji, Steven R. Lange
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Patent number: 9659670Abstract: Computer-implemented methods, computer-readable media, and systems for classifying defects detected in a memory device area on a wafer are provided.Type: GrantFiled: July 28, 2009Date of Patent: May 23, 2017Assignee: KLA-Tencor Corp.Inventors: SunYong Choi, YeonHo Pae, Ellis Chang
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Patent number: 9576861Abstract: Universal target based inspection drive metrology includes designing a plurality of universal metrology targets measurable with an inspection tool and measurable with a metrology tool, identifying a plurality of inspectable features within at least one die of a wafer using design data, disposing the plurality of universal targets within the at least one die of the wafer, each universal target being disposed at least proximate to one of the identified inspectable features, inspecting a region containing one or more of the universal targets with an inspection tool, identifying one or more anomalistic universal targets in the inspected region with an inspection tool and, responsive to the identification of one or more anomalistic universal targets in the inspected region, performing one or more metrology processes on the one or more anomalistic universal metrology targets with the metrology tool.Type: GrantFiled: November 18, 2013Date of Patent: February 21, 2017Assignee: KLA-Tencor CorporationInventors: Allen Park, Ellis Chang, Michael Adel, Kris Bhaskar, Ady Levy, Amir Widmann, Mark Wagner, Songnian Rong
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Patent number: 9518932Abstract: Methods and systems for determining one or more parameters of a wafer inspection process are provided. One method includes acquiring metrology data for a wafer generated by a wafer metrology system. The method also includes determining one or more parameters of a wafer inspection process for the wafer or another wafer based on the metrology data.Type: GrantFiled: October 17, 2014Date of Patent: December 13, 2016Assignee: KLA-Tencor Corp.Inventors: Allen Park, Craig MacNaughton, Ellis Chang
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Patent number: 9401014Abstract: Various methods and systems for utilizing design data in combination with inspection data are provided. One computer-implemented method for binning defects detected on a wafer includes comparing portions of design data proximate positions of the defects in design data space. The method also includes determining if the design data in the portions is at least similar based on results of the comparing step. In addition, the method includes binning the defects in groups such that the portions of the design data proximate the positions of the defects in each of the groups are at least similar. The method further includes storing results of the binning step in a storage medium.Type: GrantFiled: December 19, 2014Date of Patent: July 26, 2016Assignee: KLA-Tencor Technologies Corp.Inventors: Khurram Zafar, Sagar Kekare, Ellis Chang, Allen Park, Peter Rose
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Publication number: 20160196379Abstract: A metrology design and verification framework is provided, which includes methods and systems for metrology structure identification in an integrated circuit design data block, design rule checking, hierarchal design of metrology target structures to minimize random errors, and metrology design rule verification of metrology target design files. In-die metrology targets are identified using various filtering methods and/or designed as hierarchical structure within dies or outside the dies. Particularly, metrology target design files are generated, which are hierarchical in structure and compatible with design rule checks. Design rule check takes into account the hierarchical and often repetitive target designs in the verification process. Layouts may be verified using design rule checks at different levels of design rules, which may be combined to remove rule violations and errors prior to actual target production.Type: ApplicationFiled: March 4, 2014Publication date: July 7, 2016Inventors: Michael Adel, Tal Shusterman, Chen Dror, Ellis Chang
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Patent number: 9170209Abstract: Inspection guided overlay metrology may include performing a pattern search in order to identify a predetermined pattern on a semiconductor wafer, generating a care area for all instances of the predetermined pattern on the semiconductor wafer, identifying defects within generated care areas by performing an inspection scan of each of the generated care areas, wherein the inspection scan includes a low-threshold or a high sensitivity inspection scan, identifying overlay sites of the predetermined pattern of the semiconductor wafer having a measured overlay error larger than a selected overlay specification utilizing a defect inspection technique, comparing location data of the identified defects of a generated care area to location data of the identified overlay sites within the generated care area in order to identify one or more locations wherein the defects are proximate to the identified overlay sites, and generating a metrology sampling plan based on the identified locations.Type: GrantFiled: October 14, 2013Date of Patent: October 27, 2015Assignee: KLA-Tencor CorporationInventors: Ellis Chang, Amir Widmann, Allen Park
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Patent number: 9151712Abstract: A design feature in a design file including a pattern to be formed on a substrate may be selected as a metrology target, alignment target or inspection proxy. Metrology or inspection may be performed on the substrate using a printed feature on the substrate that corresponds to the design feature as a metrology target or inspection proxy.Type: GrantFiled: May 30, 2008Date of Patent: October 6, 2015Assignee: KLA-Tencor CorporationInventors: Michael Adel, Ellis Chang
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Patent number: 9087367Abstract: Methods and systems for determining design coordinates for defects detected on a wafer are provided. One method includes aligning a design for a wafer to defect review tool images for defects detected in multiple swaths on the wafer by an inspection tool, determining a position of each of the defects in design coordinates based on results of the aligning, separately determining a defect position offset for each of the multiple swaths based on the swath in which each of the defects was detected (swath correction factor), the design coordinates for each of the defects, and a position for each of the defects determined by the inspection tool, and determining design coordinates for the other defects detected in the multiple swaths by the inspection tool by applying the appropriate swath correction factor to those defects.Type: GrantFiled: August 31, 2012Date of Patent: July 21, 2015Assignee: KLA-Tencor Corp.Inventors: Ellis Chang, Michael J. Van Riet, Allen Park, Khurram Zafar, Santosh Bhattacharyya