Patents by Inventor Ellis Lee

Ellis Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7412394
    Abstract: A system for speeding up an establishment's foundation through Internet comprises a data storage device having databases built therein and an electronic hub connected to the data storage device through computer program. The electronic hub is cooperated with the data storage device, whereby is capable to communicate, examine the resource provider, save the resource provider, and match the resource provider and whereby speeds up the establishment's foundation. A method for speeding up founding establishment through Internet comprises communicating, examining the resource provider, saving the resource provider, and matching the resource provider.
    Type: Grant
    Filed: January 24, 2001
    Date of Patent: August 12, 2008
    Assignee: United Microelectronics Corp.
    Inventors: John Hsuan, Ellis Lee
  • Patent number: 6987057
    Abstract: An bonding pad structure has a passivation layer over a copper layer having a pad window to expose a portion of the copper layer, a barrier layer conformal to a profile of the pad window, and an aluminum pad located in the pad window. The metal layer can be an aluminum, aluminum alloy or aluminum dominated layer for providing a better adhesion property between the copper layer and the bonding wire.
    Type: Grant
    Filed: August 27, 2002
    Date of Patent: January 17, 2006
    Assignee: United Microelectronics Corp.
    Inventors: Ellis Lee, Yimin Huang, Tri-Rung Yew
  • Patent number: 6940146
    Abstract: An interconnect is formed on the substrate. The conductive structure at least includes a first conductive structure and a second conductive structure, which have a gap region in-between. The substrate is exposed at the gap region. A first structured dielectric layer is formed over the substrate to cover the first and the second conductive structures. The first structured dielectric layer also has a void at the gap region between the first and the second conductive structures. The void significantly extends to the whole gap region. The first structured dielectric layer also has an indent region above the void. An anti-etch layer fills the indent region of the first structured dielectric layer. As a result, the first structured dielectric layer has a substantially planar surface. A second structured dielectric layer is formed on the first structured dielectric layer and the anti-etch layer.
    Type: Grant
    Filed: September 23, 2003
    Date of Patent: September 6, 2005
    Assignee: United Microelectronics Corp.
    Inventors: Ellis Lee, Tsing-Fong Hwang
  • Patent number: 6914318
    Abstract: An interconnect is formed on the substrate. The conductive structure at least includes a first conductive structure and a second conductive structure, which have a gap region in-between. The substrate is exposed at the gap region. A first structured dielectric layer is formed over the substrate to cover the first and the second conductive structures. The first structured dielectric layer also has a void at the gap region between the first and the second conductive structures. The void significantly extends to the whole gap region. The first structured dielectric layer also has an indent region above the void. An anti-etch layer fills the indent region of the first structured dielectric layer. As a result, the first structured dielectric layer has a substantially planar surface. A second structured dielectric layer is formed on the first structured dielectric layer and the anti-etch layer.
    Type: Grant
    Filed: September 23, 2003
    Date of Patent: July 5, 2005
    Assignee: United Microelectronics Corp.
    Inventors: Ellis Lee, Tsing-Fong Hwang
  • Publication number: 20050131775
    Abstract: A system for speeding up an establishment's foundation through Internet comprises a data storage device having databases built therein and an electronic hub connected to the data storage device through computer program. The electronic hub is cooperated with the data storage device, whereby is capable to communicate, examine the resource provider, save the resource provider, and match the resource provider and whereby speeds up the establishment's foundation. A method for speeding up founding establishment through Internet comprises communicating, examining the resource provider, saving the resource provider, and matching the resource provider.
    Type: Application
    Filed: February 1, 2005
    Publication date: June 16, 2005
    Applicant: United Microelectrics Corporation
    Inventors: John Hsuan, Ellis Lee
  • Patent number: 6888247
    Abstract: An interconnect is formed on the substrate. The conductive structure at least includes a first conductive structure and a second conductive structure, which have a gap region in-between. The substrate is exposed at the gap region. A first structured dielectric layer is formed over the substrate to cover the first and the second conductive structures. The first structured dielectric layer also has a void at the gap region between the first and the second conductive structures. The void significantly extends to the whole gap region. The first structured dielectric layer also has an indent region above the void. An anti-etch layer fills the indent region of the first structured dielectric layer As a result, the first structured dielectric layer has a substantially planar surface A second structured dielectric layer is formed on the first structured dielectric layer and the anti-etch layer.
    Type: Grant
    Filed: October 5, 2001
    Date of Patent: May 3, 2005
    Assignee: United Microelectronics Corp.
    Inventors: Ellis Lee, Tsing-Fong Hwang
  • Patent number: 6794752
    Abstract: An bonding pad structure has a passivation layer over a copper layer having a pad window to expose a portion of the copper layer, a barrier layer conformal to a profile of the pad window, and an aluminum pad located in the pad window. The metal layer can be an aluminum, aluminum alloy or aluminum dominated layer for providing a better adhesion property between the copper layer and the bonding wire.
    Type: Grant
    Filed: May 23, 2001
    Date of Patent: September 21, 2004
    Assignee: United Microelectronics Corp.
    Inventors: Ellis Lee, Yimin Huang, Tri-Rung Yew
  • Publication number: 20040056359
    Abstract: An interconnect is formed on the substrate. The conductive structure at least includes a first conductive structure and a second conductive structure, which have a gap region in-between. The substrate is exposed at the gap region. A first structured dielectric layer is formed over the substrate to cover the first and the second conductive structures. The first structured dielectric layer also has a void at the gap region between the first and the second conductive structures. The void significantly extends to the whole gap region. The first structured dielectric layer also has an indent region above the void. An anti-etch layer fills the indent region of the first structured dielectric layer. As a result, the first structured dielectric layer has a substantially planar surface. A second structured dielectric layer is formed on the first structured dielectric layer and the anti-etch layer.
    Type: Application
    Filed: September 23, 2003
    Publication date: March 25, 2004
    Inventors: Ellis Lee, Tsing-Fong Hwang
  • Publication number: 20040056358
    Abstract: An interconnect is formed on the substrate. The conductive structure at least includes a first conductive structure and a second conductive structure, which have a gap region in-between. The substrate is exposed at the gap region. A first structured dielectric layer is formed over the substrate to cover the first and the second conductive structures. The first structured dielectric layer also has a void at the gap region between the first and the second conductive structures. The void significantly extends to the whole gap region. The first structured dielectric layer also has an indent region above the void. An anti-etch layer fills the indent region of the first structured dielectric layer. As a result, the first structured dielectric layer has a substantially planar surface. A second structured dielectric layer is formed on the first structured dielectric layer and the anti-etch layer.
    Type: Application
    Filed: September 23, 2003
    Publication date: March 25, 2004
    Inventors: Ellis Lee, Tsing-Fong Hwang
  • Patent number: 6657283
    Abstract: Structures for reducing relative stress between HDP layer and passivation layer are proposed by the invention, where the HDP layer is formed by high density plasma and the passivation layer is a conventional passivation layer. The invention provides some structures that can be divided into two categories: one, a low stress passivation layer is directly formed on a HDP layer; another, a low stress layer is formed between passivation layer and HDP layer to reduce relative layer that between any two adjacent layers. Therefore, it is crystal-clear that possible structures of the invention comprise following varieties: First, a low stress passivation layer is located between a passivation layer and a HDP layer. Second, a lower stress passivation layer directly locates on a HDP layer. Third, a low stress layer is formed between a passivation layer and a HDP layer.
    Type: Grant
    Filed: June 13, 2002
    Date of Patent: December 2, 2003
    Assignee: United Microelectronics Corp.
    Inventors: Ellis Lee, Ing-Tang Chen, Horng-Bor Lu
  • Publication number: 20030006505
    Abstract: An bonding pad structure has a passivation layer over a copper layer having a pad window to expose a portion of the copper layer, a barrier layer conformal to a profile of the pad window, and an aluminum pad located in the pad window. The metal layer can be an aluminum, aluminum alloy or aluminum dominated layer for providing a better adhesion property between the copper layer and the bonding wire.
    Type: Application
    Filed: August 27, 2002
    Publication date: January 9, 2003
    Inventors: Ellis Lee, Yimin Huang, Tri-Rung Yew
  • Publication number: 20020195688
    Abstract: Structures for reducing relative stress between HDP layer and passivation layer are proposed by the invention, where the HDP layer is formed by high density plasma and the passivation layer is a conventional passivation layer. The invention provides some structures that can be divided into two categories: one, a low stress passivation layer is directly formed on a HDP layer; another, a low stress layer is formed between passivation layer and HDP layer to reduce relative layer that between any two adjacent layers. Therefore, it is crystal-clear that possible structures of the invention comprise following varieties: First, a low stress passivation layer is located between a passivation layer and a HDP layer. Second, a lower stress passivation layer directly locates on a HDP layer. Third, a low stress layer is formed between a passivation layer and a HDP layer.
    Type: Application
    Filed: June 13, 2002
    Publication date: December 26, 2002
    Inventors: Ellis Lee, Ing-Tang Chen, Horng-Bor Lu
  • Patent number: 6492732
    Abstract: An interconnect structure has a substrate having devices already formed thereon. A dielectric layer covers over the substrate. A conductive structure having at least two substructure separated by an air gap is formed on the dielectric layer. A capping layer covers the conductive structure and the air gap. The capping layer at a portion above the air gap also fills into the air gap by a predetermined distance. The air gap may also extend into the dielectric layer to have a greater height. An etching stop layer is formed on the capping layer. An inter-metal dielectric layer is formed on the etching stop layer. The inter-metal dielectric layer, the etching stop layer and the capping layer are patterned to form an opening that exposes a top surface of the conductive structure.
    Type: Grant
    Filed: May 4, 2001
    Date of Patent: December 10, 2002
    Assignee: United Microelectronics Corp.
    Inventors: Ellis Lee, Shih-Wei Sun
  • Patent number: 6492256
    Abstract: An interconnect structure has a substrate having devices already formed thereon. A dielectric layer covers over the substrate. A conductive structure having at least two substructure separated by an air gap is formed on the dielectric layer. A capping layer covers the conductive structure and the air gap. The capping layer at a portion above the air gap also fills into the air gap by a predetermined distance. The air gap may also extend into the dielectric layer to have a greater height. An etching stop layer is formed on the capping layer. An inter-metal dielectric layer is formed on the etching stop layer. The inter-metal dielectric layer, the etching stop layer and the capping layer are patterned to form an opening that exposes a top surface of the conductive structure.
    Type: Grant
    Filed: March 15, 2002
    Date of Patent: December 10, 2002
    Assignee: United Microelectronics Corp.
    Inventors: Ellis Lee, Shih-Wei Sun
  • Publication number: 20020163082
    Abstract: An interconnect structure has a substrate having devices already formed thereon. A dielectric layer covers over the substrate. A conductive structure having at least two substructure separated by an air gap is formed on the dielectric layer. A capping layer covers the conductive structure and the air gap. The capping layer at a portion above the air gap also fills into the air gap by a predetermined distance. The air gap may also extend into the dielectric layer to have a greater height. An etching stop layer is formed on the capping layer. An inter-metal dielectric layer is formed on the etching stop layer. The inter-metal dielectric layer, the etching stop layer and the capping layer are patterned to form an opening that exposes a top surface of the conductive structure.
    Type: Application
    Filed: March 15, 2002
    Publication date: November 7, 2002
    Inventors: Ellis Lee, Shih-Wei Sun
  • Publication number: 20020099558
    Abstract: A system for speeding up an establishment's foundation through Internet comprises a data storage device having databases built therein and an electronic hub connected to the data storage device through computer program. The electronic hub is cooperated with the data storage device, whereby is capable to communicate, examine the resource provider, save the resource provider, and match the resource provider and whereby speeds up the establishment's foundation. A method for speeding up founding establishment through Internet comprises communicating, examining the resource provider, saving the resource provider, and matching the resource provider.
    Type: Application
    Filed: January 24, 2001
    Publication date: July 25, 2002
    Applicant: United Microelectronics Corp.
    Inventors: John Hsuan, Ellis Lee
  • Publication number: 20020014679
    Abstract: An interconnect is formed on the substrate. The conductive structure at least includes a first conductive structure and a second conductive structure, which have a gap region in-between. The substrate is exposed at the gap region. A first structured dielectric layer is formed over the substrate to cover the first and the second conductive structures. The first structured dielectric layer also has a void at the gap region between the first and the second conductive structures. The void significantly extends to the whole gap region. The first structured dielectric layer also has an indent region above the void. An anti-etch layer fills the indent region of the first structured dielectric layer As a result, the first structured dielectric layer has a substantially planar surface A second structured dielectric layer is formed on the first structured dielectric layer and the anti-etch layer.
    Type: Application
    Filed: October 5, 2001
    Publication date: February 7, 2002
    Inventors: Ellis Lee, Tsing-Fong Hwang
  • Publication number: 20010022403
    Abstract: An bonding pad structure has a passivation layer over a copper layer having a pad window to expose a portion of the copper layer, a barrier layer conformal to a profile of the pad window, and an aluminum pad located in the pad window. The metal layer can be an aluminum, aluminum alloy or aluminum dominated layer for providing a better adhesion property between the copper layer and the bonding wire.
    Type: Application
    Filed: May 23, 2001
    Publication date: September 20, 2001
    Inventors: Ellis Lee, Yimin Huang, Tri-Rung Yew
  • Publication number: 20010016412
    Abstract: An interconnect structure has a substrate having devices already formed thereon. A dielectric layer covers over the substrate. A conductive structure having at least two substructure separated by an air gap is formed on the dielectric layer. A capping layer covers the conductive structure and the air gap. The capping layer at a portion above the air gap also fills into the air gap by a predetermined distance. The air gap may also extend into the dielectric layer to have a greater height. An etching stop layer is formed on the capping layer. An inter-metal dielectric layer is formed on the etching stop layer. The inter-metal dielectric layer, the etching stop layer and the capping layer are patterned to form an opening that exposes a top surface of the conductive structure.
    Type: Application
    Filed: May 4, 2001
    Publication date: August 23, 2001
    Inventors: Ellis Lee, Shih-Wei Sun
  • Patent number: 6245635
    Abstract: A method of fabricating a shallow trench isolation includes formation of a polishing stop layer. The polishing stop layer is formed in a fill material by performing ion implantation to implant atoms in the fill material. The depth of the polishing stop layer can be controlled by the energy of the implanted atoms. The polishing stop layer prevents the fill material from being dished by chemical-mechanical polishing. The polishing stop layer also prevents scratches from forming in the surface of the fill material, which is used to form isolation regions.
    Type: Grant
    Filed: November 30, 1998
    Date of Patent: June 12, 2001
    Assignee: United Microelectronics Corp.
    Inventor: Ellis Lee