Patents by Inventor Ellis Lee
Ellis Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10880284Abstract: Disclosed are various embodiments for repurposing limited-functionality networked devices as authentication factors. In one embodiment, an authentication service identifies a limited-functionality networked device associated with an account and communicatively coupled to the network. The limited-functionality networked device is configured to perform a first function upon a predefined user interaction. The service configures the limited-functionality networked device to perform a second function based at least in part on the predefined user interaction. The service determines that the predefined user interaction has been performed by a user with respect to the limited-functionality networked device. The service authenticates the user at a client device for access to the account based at least in part on the predefined user interaction having been performed.Type: GrantFiled: August 19, 2016Date of Patent: December 29, 2020Assignee: AMAZON TECHNOLOGIES, INC.Inventors: Daniel Wade Hitchcock, Bharath Kumar Bhimanaik, Robert Ellis Lee
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Patent number: 10803164Abstract: Disclosed are various embodiments for validating that relying parties of a federated identity provider have correctly implemented sign-out functionality. In one approach, a network page is received from a network site that is operated by a relying party of a federated identity provider. It is then determined whether the network page includes code that properly implements a sign-out from the federated identity provider. An action is initiated in response to determining that the network page does not include code that properly implements the sign-out from the federated identity provider.Type: GrantFiled: September 13, 2018Date of Patent: October 13, 2020Assignee: AMAZON TECHNOLOGIES, INC.Inventors: Jon Arron McClintock, David Scott Cleckley, Jr., Robert Ellis Lee, Annabelle Richard Backman
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Patent number: 10333946Abstract: Disclosed are various embodiments for distributing and verifying ephemeral security credentials of variable entropy across channels of communication of variable levels of security assurance. In one embodiment, a security credential is generated for a user account. A subset of a set of communication channels associated with the user account is determined based at least in part on respective measures of entropy and/or security assurance corresponding to individual ones of the set of communication channels. The security credential is divided into multiple portions. A corresponding portion of the portions is sent across individual channels of subset of channels. A client computing device is authenticated for access to the user account based at least in part on receiving the portions of the security credential.Type: GrantFiled: June 22, 2016Date of Patent: June 25, 2019Assignee: Amazon Technologies, Inc.Inventors: Daniel Wade Hitchcock, Bharath Kumar Bhimanaik, Robert Ellis Lee
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Publication number: 20190012454Abstract: Disclosed are various embodiments for validating that relying parties of a federated identity provider have correctly implemented sign-out functionality. In one approach, a network page is received from a network site that is operated by a relying party of a federated identity provider. It is then determined whether the network page includes code that properly implements a sign-out from the federated identity provider. An action is initiated in response to determining that the network page does not include code that properly implements the sign-out from the federated identity provider.Type: ApplicationFiled: September 13, 2018Publication date: January 10, 2019Inventors: JON ARRON MCCLINTOCK, DAVID SCOTT CLECKLEY, JR., ROBERT ELLIS LEE, ANNABELLE RICHARD BACKMAN
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Patent number: 10095860Abstract: Disclosed are various embodiments for validating that relying parties of a federated identity provider have correctly implemented sign-out functionality. In one approach, a network page is received from a network site that is operated by a relying party of a federated identity provider. It is then determined whether the network page includes code that properly implements a sign-out from the federated identity provider. An action is initiated in response to determining that the network page does not include code that properly implements the sign-out from the federated identity provider.Type: GrantFiled: December 9, 2015Date of Patent: October 9, 2018Assignee: Amazon Technologies, Inc.Inventors: Jon Arron McClintock, David Scott Cleckley, Jr., Robert Ellis Lee, Annabelle Richard Backman
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Patent number: 7412394Abstract: A system for speeding up an establishment's foundation through Internet comprises a data storage device having databases built therein and an electronic hub connected to the data storage device through computer program. The electronic hub is cooperated with the data storage device, whereby is capable to communicate, examine the resource provider, save the resource provider, and match the resource provider and whereby speeds up the establishment's foundation. A method for speeding up founding establishment through Internet comprises communicating, examining the resource provider, saving the resource provider, and matching the resource provider.Type: GrantFiled: January 24, 2001Date of Patent: August 12, 2008Assignee: United Microelectronics Corp.Inventors: John Hsuan, Ellis Lee
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Patent number: 6987057Abstract: An bonding pad structure has a passivation layer over a copper layer having a pad window to expose a portion of the copper layer, a barrier layer conformal to a profile of the pad window, and an aluminum pad located in the pad window. The metal layer can be an aluminum, aluminum alloy or aluminum dominated layer for providing a better adhesion property between the copper layer and the bonding wire.Type: GrantFiled: August 27, 2002Date of Patent: January 17, 2006Assignee: United Microelectronics Corp.Inventors: Ellis Lee, Yimin Huang, Tri-Rung Yew
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Patent number: 6940146Abstract: An interconnect is formed on the substrate. The conductive structure at least includes a first conductive structure and a second conductive structure, which have a gap region in-between. The substrate is exposed at the gap region. A first structured dielectric layer is formed over the substrate to cover the first and the second conductive structures. The first structured dielectric layer also has a void at the gap region between the first and the second conductive structures. The void significantly extends to the whole gap region. The first structured dielectric layer also has an indent region above the void. An anti-etch layer fills the indent region of the first structured dielectric layer. As a result, the first structured dielectric layer has a substantially planar surface. A second structured dielectric layer is formed on the first structured dielectric layer and the anti-etch layer.Type: GrantFiled: September 23, 2003Date of Patent: September 6, 2005Assignee: United Microelectronics Corp.Inventors: Ellis Lee, Tsing-Fong Hwang
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Patent number: 6914318Abstract: An interconnect is formed on the substrate. The conductive structure at least includes a first conductive structure and a second conductive structure, which have a gap region in-between. The substrate is exposed at the gap region. A first structured dielectric layer is formed over the substrate to cover the first and the second conductive structures. The first structured dielectric layer also has a void at the gap region between the first and the second conductive structures. The void significantly extends to the whole gap region. The first structured dielectric layer also has an indent region above the void. An anti-etch layer fills the indent region of the first structured dielectric layer. As a result, the first structured dielectric layer has a substantially planar surface. A second structured dielectric layer is formed on the first structured dielectric layer and the anti-etch layer.Type: GrantFiled: September 23, 2003Date of Patent: July 5, 2005Assignee: United Microelectronics Corp.Inventors: Ellis Lee, Tsing-Fong Hwang
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Publication number: 20050131775Abstract: A system for speeding up an establishment's foundation through Internet comprises a data storage device having databases built therein and an electronic hub connected to the data storage device through computer program. The electronic hub is cooperated with the data storage device, whereby is capable to communicate, examine the resource provider, save the resource provider, and match the resource provider and whereby speeds up the establishment's foundation. A method for speeding up founding establishment through Internet comprises communicating, examining the resource provider, saving the resource provider, and matching the resource provider.Type: ApplicationFiled: February 1, 2005Publication date: June 16, 2005Applicant: United Microelectrics CorporationInventors: John Hsuan, Ellis Lee
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Patent number: 6888247Abstract: An interconnect is formed on the substrate. The conductive structure at least includes a first conductive structure and a second conductive structure, which have a gap region in-between. The substrate is exposed at the gap region. A first structured dielectric layer is formed over the substrate to cover the first and the second conductive structures. The first structured dielectric layer also has a void at the gap region between the first and the second conductive structures. The void significantly extends to the whole gap region. The first structured dielectric layer also has an indent region above the void. An anti-etch layer fills the indent region of the first structured dielectric layer As a result, the first structured dielectric layer has a substantially planar surface A second structured dielectric layer is formed on the first structured dielectric layer and the anti-etch layer.Type: GrantFiled: October 5, 2001Date of Patent: May 3, 2005Assignee: United Microelectronics Corp.Inventors: Ellis Lee, Tsing-Fong Hwang
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Patent number: 6794752Abstract: An bonding pad structure has a passivation layer over a copper layer having a pad window to expose a portion of the copper layer, a barrier layer conformal to a profile of the pad window, and an aluminum pad located in the pad window. The metal layer can be an aluminum, aluminum alloy or aluminum dominated layer for providing a better adhesion property between the copper layer and the bonding wire.Type: GrantFiled: May 23, 2001Date of Patent: September 21, 2004Assignee: United Microelectronics Corp.Inventors: Ellis Lee, Yimin Huang, Tri-Rung Yew
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Publication number: 20040056359Abstract: An interconnect is formed on the substrate. The conductive structure at least includes a first conductive structure and a second conductive structure, which have a gap region in-between. The substrate is exposed at the gap region. A first structured dielectric layer is formed over the substrate to cover the first and the second conductive structures. The first structured dielectric layer also has a void at the gap region between the first and the second conductive structures. The void significantly extends to the whole gap region. The first structured dielectric layer also has an indent region above the void. An anti-etch layer fills the indent region of the first structured dielectric layer. As a result, the first structured dielectric layer has a substantially planar surface. A second structured dielectric layer is formed on the first structured dielectric layer and the anti-etch layer.Type: ApplicationFiled: September 23, 2003Publication date: March 25, 2004Inventors: Ellis Lee, Tsing-Fong Hwang
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Publication number: 20040056358Abstract: An interconnect is formed on the substrate. The conductive structure at least includes a first conductive structure and a second conductive structure, which have a gap region in-between. The substrate is exposed at the gap region. A first structured dielectric layer is formed over the substrate to cover the first and the second conductive structures. The first structured dielectric layer also has a void at the gap region between the first and the second conductive structures. The void significantly extends to the whole gap region. The first structured dielectric layer also has an indent region above the void. An anti-etch layer fills the indent region of the first structured dielectric layer. As a result, the first structured dielectric layer has a substantially planar surface. A second structured dielectric layer is formed on the first structured dielectric layer and the anti-etch layer.Type: ApplicationFiled: September 23, 2003Publication date: March 25, 2004Inventors: Ellis Lee, Tsing-Fong Hwang
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Patent number: 6657283Abstract: Structures for reducing relative stress between HDP layer and passivation layer are proposed by the invention, where the HDP layer is formed by high density plasma and the passivation layer is a conventional passivation layer. The invention provides some structures that can be divided into two categories: one, a low stress passivation layer is directly formed on a HDP layer; another, a low stress layer is formed between passivation layer and HDP layer to reduce relative layer that between any two adjacent layers. Therefore, it is crystal-clear that possible structures of the invention comprise following varieties: First, a low stress passivation layer is located between a passivation layer and a HDP layer. Second, a lower stress passivation layer directly locates on a HDP layer. Third, a low stress layer is formed between a passivation layer and a HDP layer.Type: GrantFiled: June 13, 2002Date of Patent: December 2, 2003Assignee: United Microelectronics Corp.Inventors: Ellis Lee, Ing-Tang Chen, Horng-Bor Lu
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Publication number: 20030006505Abstract: An bonding pad structure has a passivation layer over a copper layer having a pad window to expose a portion of the copper layer, a barrier layer conformal to a profile of the pad window, and an aluminum pad located in the pad window. The metal layer can be an aluminum, aluminum alloy or aluminum dominated layer for providing a better adhesion property between the copper layer and the bonding wire.Type: ApplicationFiled: August 27, 2002Publication date: January 9, 2003Inventors: Ellis Lee, Yimin Huang, Tri-Rung Yew
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Publication number: 20020195688Abstract: Structures for reducing relative stress between HDP layer and passivation layer are proposed by the invention, where the HDP layer is formed by high density plasma and the passivation layer is a conventional passivation layer. The invention provides some structures that can be divided into two categories: one, a low stress passivation layer is directly formed on a HDP layer; another, a low stress layer is formed between passivation layer and HDP layer to reduce relative layer that between any two adjacent layers. Therefore, it is crystal-clear that possible structures of the invention comprise following varieties: First, a low stress passivation layer is located between a passivation layer and a HDP layer. Second, a lower stress passivation layer directly locates on a HDP layer. Third, a low stress layer is formed between a passivation layer and a HDP layer.Type: ApplicationFiled: June 13, 2002Publication date: December 26, 2002Inventors: Ellis Lee, Ing-Tang Chen, Horng-Bor Lu
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Patent number: 6492256Abstract: An interconnect structure has a substrate having devices already formed thereon. A dielectric layer covers over the substrate. A conductive structure having at least two substructure separated by an air gap is formed on the dielectric layer. A capping layer covers the conductive structure and the air gap. The capping layer at a portion above the air gap also fills into the air gap by a predetermined distance. The air gap may also extend into the dielectric layer to have a greater height. An etching stop layer is formed on the capping layer. An inter-metal dielectric layer is formed on the etching stop layer. The inter-metal dielectric layer, the etching stop layer and the capping layer are patterned to form an opening that exposes a top surface of the conductive structure.Type: GrantFiled: March 15, 2002Date of Patent: December 10, 2002Assignee: United Microelectronics Corp.Inventors: Ellis Lee, Shih-Wei Sun
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Patent number: 6492732Abstract: An interconnect structure has a substrate having devices already formed thereon. A dielectric layer covers over the substrate. A conductive structure having at least two substructure separated by an air gap is formed on the dielectric layer. A capping layer covers the conductive structure and the air gap. The capping layer at a portion above the air gap also fills into the air gap by a predetermined distance. The air gap may also extend into the dielectric layer to have a greater height. An etching stop layer is formed on the capping layer. An inter-metal dielectric layer is formed on the etching stop layer. The inter-metal dielectric layer, the etching stop layer and the capping layer are patterned to form an opening that exposes a top surface of the conductive structure.Type: GrantFiled: May 4, 2001Date of Patent: December 10, 2002Assignee: United Microelectronics Corp.Inventors: Ellis Lee, Shih-Wei Sun
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Patent number: D1016880Type: GrantFiled: August 22, 2023Date of Patent: March 5, 2024Assignee: GOOGLE LLCInventors: Mark Woolhiser Huang, Sung Bai, Maj Isabelle Olsson, Albert Ellis Lee