Patents by Inventor Ellis Robinson Giles

Ellis Robinson Giles has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11868421
    Abstract: An embodiment of a system for determining the disposition of a hyperdocument and hyperdocument requests using a trained artificial neural network, including an information source, a requesting application, and a server containing a trained artificial neural network (ANN), the ANN being capable of evaluating the information, and providing results reflecting the evaluation to a requesting application is described.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: January 9, 2024
    Inventor: Ellis Robinson Giles
  • Patent number: 11756618
    Abstract: A log structure is created in persistent memory using hardware support in memory controller or software supported with additional instructions. Writes to persistent memory locations are streamed to the log and written to their corresponding memory location in cache hierarchy. An added victim cache for persistent memory addresses catches cache evictions, which would corrupt open transactions. On the completion of a group of atomic persistent memory operations, the log is closed and the persistent values in the cache can be copied to their source persistent memory location and the log cleaned.
    Type: Grant
    Filed: June 28, 2021
    Date of Patent: September 12, 2023
    Inventors: Ellis Robinson Giles, Peter Joseph Varman
  • Patent number: 11049562
    Abstract: Emerging byte-addressable persistent memory technologies, generically referred to as Storage Class Memory, offer performance advantages and access similar to Dynamic Random Access Memory while having the persistence of disk. Unifying storage and memory into a memory tier that can be accessed directly requires additional burden to ensure that groups of memory operations to persistent or nonvolatile memory locations are performed sequentially, atomically, and not caught in the cache hierarchy. The present invention provides a lightweight solution for the atomicity and durability of write operations to nonvolatile memory, while simultaneously supporting fast paths through the cache hierarchy to memory. The invention includes a hardware-supported solution with modifications to the memory hierarchy comprising a victim cache and additional memory controller logic.
    Type: Grant
    Filed: December 24, 2018
    Date of Patent: June 29, 2021
    Inventors: Ellis Robinson Giles, Peter Joseph Varman
  • Patent number: 10956324
    Abstract: Persistent Memory, byte-addressable non-volatile memory technologies, offer performance advantages and access similar to Dynamic Random Access Memory while having the persistence of disk. Hardware Transactional Memory support, originally designed for DRAM concurrency control, can corrupt persistent memory transactions due to cache evictions before system failure. Unifying storage and memory on the main-memory bus and accessed directly while using HTM for concurrency control has previously required the additional burden of changes to processors to prevent possible data corruption. The present invention provides a solution for the durability of transactions to persistent memory while using HTM as a concurrency control mechanism, without any changes to processors or cache-coherency mechanisms. The invention includes a software only method and system that provides durability and ordering of HTM transactions to persistent memory.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: March 23, 2021
    Inventors: Ellis Robinson Giles, Peter Joseph Varman
  • Patent number: 10163510
    Abstract: Emerging byte-addressable persistent memory technologies, generically referred to as Storage Class Memory, offer performance advantages and access similar to Dynamic Random Access Memory while having the persistence of disk. Unifying storage and memory into a memory tier that can be accessed directly requires additional burden to ensure that groups of memory operations to persistent or nonvolatile memory locations are performed sequentially, atomically, and not caught in the cache hierarchy. The present invention provides a lightweight solution for the atomicity and durability of write operations to nonvolatile memory, while simultaneously supporting fast paths through the cache hierarchy to memory. The invention includes a hardware-supported solution with modifications to the memory hierarchy comprising a victim cache and additional memory controller logic.
    Type: Grant
    Filed: August 11, 2014
    Date of Patent: December 25, 2018
    Inventors: Ellis Robinson Giles, Peter Joseph Varman
  • Patent number: 7403929
    Abstract: An embodiment of a computer implemented method for determining the disposition of a hyperdocument includes retrieving a hyperdocument from an information source, providing information about content of the hyperdocument to a trained artificial neural network (ANN), the ANN being capable of evaluating the information and providing results reflecting the evaluation, and determining the disposition of the hyperdocument based upon results of the ANN.
    Type: Grant
    Filed: July 22, 2005
    Date of Patent: July 22, 2008
    Inventors: Ellis Robinson Giles, Vick Forrest Giles
  • Patent number: D708255
    Type: Grant
    Filed: July 26, 2011
    Date of Patent: July 1, 2014
    Inventors: Chad Alan Stevens, Ellis Robinson Giles
  • Patent number: D759754
    Type: Grant
    Filed: June 28, 2014
    Date of Patent: June 21, 2016
    Inventors: Chad Alan Stevens, Ellis Robinson Giles
  • Patent number: D772979
    Type: Grant
    Filed: April 4, 2016
    Date of Patent: November 29, 2016
    Inventors: Chad Alan Stevens, Ellis Robinson Giles