Abstract: A redundant electric fuse circuit is provided that includes a plurality of fuses coupled in series and each having a fuse control device operable for generating a current through each fuse sufficient to blow the fuse. A first fuse control signal is activated to generate a sufficient current through one of the fuses to blow the fuse. A second fuse control signal is activated to generate a sufficient current through the other fuse to blow that fuse. The electric fuse circuit provides redundancy thereby increasing the yield of integrated circuits by reducing the probability that a defective fuse (i.e., a fuse that reforms after blowing) will cause a fatal defect in the integrated circuit.

Abstract: A circuit and method are disclosed for controlling bootstrap circuitry that boosts a voltage level appearing on word lines of a dynamic random access memory device. During execution of a memory access operation, the circuit is adapted to enable the bootstrap circuitry a period of time following the memory device's sense amplifiers initially powering up. The circuit senses when the voltage appearing on a select bit line crosses a predetermined voltage level, and enables the bootstrap circuitry thereafter. In this way, a period of time elapses between the sense amplifiers turning on and the activation of the bootstrap circuitry, thereby reducing noise introduced from the sense amplifiers turning on from impacting the operation of the bootstrap circuitry.

Abstract: A reference voltage generator that may be utilized in an integrated circuit such as a dynamic random access memory (DRAM) includes a voltage divider connected to a voltage supply and a feedback buffer amplifier. The voltage divider, which determines the reference voltage, supplies at least one voltage output signal to the feedback buffer amplifier under control of a feedback control signal supplied by the feedback buffer amplifier. In at least one embodiment, the reference voltage generator further includes a delay element coupled between the voltage divider and the feedback buffer amplifier in-line with the feedback control signal and a low impedance output buffer that receives the voltage output signal from the voltage divider and supplies the reference voltage at an output node. When the reference voltage generator is implemented within a dynamic random access memory, the reference voltage is supplied to the reference plates of bit storage capacitors within the memory cells.

Abstract: Composite layers of titanium silicide and polysilicon define a fuse resistor within a programmable fuse element that increases its resistance from about 50 ohms in the unprogrammed state to about 250 K-ohms in the programmed state by creating a discontinuity in the silicide layer immediately over a PN junction in the polysilicon layer. The resistance of the fuse resistor in the programmed state is determined by the reverse-biased diode characteristic of the PN junction. Portions of a metallic layer overlie portions of the fuse resistor except at the site of the PN junction in the polysilicon layer so that the silicide is preferentially heated immediately above the PN junction to cause the discontinuity to occur at that site. The metallic layer portions serve both as a heat sink for the underlying portions of the silicide layer and as electrical connections to the fuse resistor.

Abstract: A semiconductor read only memory device includes memory cells arranged in a matrix of rows and columns; word lines crossing the matrix, wherein one word line is connected to each row of memory cells; and bit lines interdigitated with column lines and positioned such that each column of memory cells is between a bit line and a column line. The matrix is subdivided into cells, where each cell has four memory cells arranged symmetrically about a bit line in two rows and two columns. All four of the cells are connected to the bit line at a common electrical node, wherein selected cells are connected to a column line. The memory device also includes a row select driver for selecting memory cells in a single row; a column select driver for selecting a single column line; and circuitry for selecting one of the bit lines adjacent to a column line.