Abstract: In an I/O driver, noise reduction is achieved while maintaining good performance, by providing a conventional output driver leg and a secondary output driver leg, the primary output driver leg comprising a primary predriver and a primary output driver, and the secondary output driver leg comprising a secondary output driver having a common output with the primary output driver, wherein feedback from the common output is fed through a pair of pass gates that control the secondary output driver.

Abstract: Bandgap voltage reference circuitry capable of operating at very low power supply voltages. The current source for driving the core bandgap voltage reference is implemented with insulated gate field effect transistors having low threshold voltages. Voltage clamp circuitry protects the transistors from power supply voltage variations rising above a predetermined clamp voltage. An output amplifier with output biasing circuitry having a circuit structure similar to that of the core bandgap voltage reference ensures that the bandgap reaches the intended steady state of operation.

Abstract: A unique number is formed with logic states from a static random access memory (SRAM), which is laid out to be balanced so that memory cells within the SRAM assume a non-random logic state when power is applied to the SRAM. The unique number is formed by grounding the word lines and bit lines before power is applied to the memory cells, applying power to the memory cells to assume the non-random logic state, reading the non-random logic states held by the memory cells, and forming the unique number from the logic states read from the memory cells.

Abstract: A unique number is formed with logic states from a static random access memory (SRAM), which is laid out to be balanced so that memory cells within the SRAM assume a non-random logic state when power is applied to the SRAM. The unique number is formed by grounding the word lines and bit lines before power is applied to the memory cells, applying power to the memory cells to assume the non-random logic state, reading the non-random logic states held by the memory cells, and forming the unique number from the logic states read from the memory cells.

Abstract: An I/O circuit includes load sense and active noise reduction features that result in high speed output signal transitions with very low noise. Capacitive feedback control circuitry controls the point and time at which feedback capacitors are applied to the gate drive of the I/O circuit output stage. Active device feedback control controls the output stage gate drive.

Abstract: An I/O circuit includes load sense and active noise reduction features that result in high speed output signal transitions with very low noise. Capacitive feedback control circuitry controls the point and time at which feedback capacitors are applied to the gate drive of the I/O circuit output stage. Active device feedback control controls the output stage gate drive.

Abstract: A unique number is formed with logic states from a static random access memory (SRAM), which is laid out to be balanced so that memory cells within the SRAM assume a non-random logic state when power is applied to the SRAM. The unique number is formed by grounding the word lines and bit lines before power is applied to the memory cells, applying power to the memory cells to assume the non-random logic state, reading the non-random logic states held by the memory cells, and forming the unique number from the logic states read from the memory cells.

Abstract: An automated method for checking electrostatic discharge (ESD) guidelines ensures that a sufficient number of ESD protection cells have been provided in the neighborhood of each pad in an integrated circuit design to ensure adequate current sinking and voltage clamping during the occurrence of an ESD event.

Abstract: A static random access memory (SRAM) is laid out to be balanced so that, when power is applied to the SRAM, the cells of the SRAM have no preferred logic state. In addition, the SRAM is fabricated in a process the emphasizes mismatches so that each individual cell assumes a non-random logic state when power is applied.

Abstract: A static random access memory (SRAM) is laid out to be balanced so that, when power is applied to the SRAM, the cells of the SRAM have no preferred logic state, In addition, the SRAM is fabricated in a process the emphasizes mismatches so that each individual cell assumes a non-random logic state when power is applied.