Abstract: A unique number is formed with logic states from a static random access memory (SRAM), which is laid out to be balanced so that memory cells within the SRAM assume a non-random logic state when power is applied to the SRAM. The unique number is formed by grounding the word lines and bit lines before power is applied to the memory cells, applying power to the memory cells to assume the non-random logic state, reading the non-random logic states held by the memory cells, and forming the unique number from the logic states read from the memory cells.

Abstract: In an I/O circuit, noise reduction and power savings are achieved by providing feedback from the output of the I/O driver to control the current through the pre-driver and thereby the current through the driver transistors after a non-zero time delay following a low to high or high to low data signal change.

Abstract: In an I/O driver that includes a cascoded pair of PMOS driver transistors connected to a pair of cascaded NMOS driver transistors and that defines a pad output between the PMOS and NMOS driver transistors, a method of providing the CMOS I/O driver with over-voltage and back-drive protection includes providing circuitry for charging the wells of the PMOS transistors either to VDDIO during normal voltage mode by making use of the power supply, or to a common voltage during over-voltage and back-drive operation using the pad voltage.

Abstract: Anti-pirate circuitry is provided for combating the theft of intellectual property contained with semiconductor integrated circuits. The anti-pirate circuit includes a unique number generator that provides a multi-bit die ID data string that is unique to the integrated circuit associated with the anti-pirate circuit. One time programmable (OTP) EPROM circuitry reads the die ID data string at wafer sort and writes the data content to nonvolatile memory. During a subsequent verification cycle, ID comparator circuitry compares the data string provided by the unique number generator to the stored contents of the nonvolatile memory. If the comparison results in a mismatch between more than a predefined number of bits, then the integrated circuit associated with the anti-pirate circuit is not enabled for operation.

Abstract: In a receiver input back-drive protection circuit and method, a pass gate is provided between the high pad voltage and the receiver input and a clamping circuit is provided, to present a reduced voltage to the receiver input during stress mode.

Abstract: An integrated, non-volatile memory protect register is provided for the memory array of a monolithic integrated circuit device. The memory array includes a plurality of programmable data storage registers, each having an associated address. The storage register addresses define the storage registers sequentially from an initial register in the array to a final register in the array. The memory protect register stores the address of a preselected storage register in the array. All registers in the array having addresses equal to or greater than the address of the preselected register are protected from any write operation. This address can be "locked" into the memory protect register to provide permanent data security to all protected registers.

Abstract: Circuitry for serial read memory access utilizing a random starting address is disclosed. Fast read access is provided without upsetting the original data pattern stored in the memory core if the sequential read is terminated in midstream. After the last memory address is reached, the access automatically rolls over to the first address. The circuit provides both random and sequential access functions and allows the memory to be used as a shift register of variable length.

Abstract: A compact, nonvolatile, zero static power, electrically alterable, bistable CMOS latch device is fabricated with single layer of polysilicon. The single polysilicon layer forms the floating gates of the nonvolatile elements of the device. The control gates are formed in the substrate by buried N+ diffusions and are separated from their respective floating gates by a thin oxide dielectric. The circuit can be designed to power-up in a preferred mode even before any programming operation has been performed on it. Thereafter, the circuit is available to be programmed to either of its two stable states. After the programming operation is completed and the circuit is latched to one of its two stable states, the fields across the thin oxide dielectrics are minimal and virtually no read disturb condition exist. Thus, the latch also offers excellent data retention characteristics.

Abstract: A circuit for regulating the internal programming voltage (Vpp) supplied to an integrated circuit memory device. The invention limits the internal programming voltage to a maximum value no greater than the field assisted breakdown voltage of on-chip transistors and/or the field transistor threshold voltage. Representatives of the several different types of transistors provided on an integrated circuit substrate are incorporated into the voltage regulating circuit. The regulator transistors are placed in the circuit in such a way that they are designed to break down first in the event of an excessive internal programming voltage (Vpp). In this way, the regulator transistors limit the voltage sent to the operating circuitry of the integrated circuit.

Abstract: Anti-pirate circuitry is provided for combating the theft of intellectual property contained with semiconductor integrated circuits. The anti-pirate circuit includes a unique number generator that provides a multi-bit die ID data string that is unique to the integrated circuit associated with the anti-pirate circuit. One time programmable (OTP) EPROM circuitry reads the die ID data string at wafer sort and writes the data content to nonvolatile memory. During a subsequent verification cycle, ID comparator circuitry compares the data string provided by the unique number generator to the stored contents of the nonvolatile memory. If the comparison results in a mismatch between more than a predefined number of bits, then the integrated circuit associated with the anti-pirate circuit is not enabled for operation.