Patents by Inventor (Elton) ZhiYong Zheng

(Elton) ZhiYong Zheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250261245
    Abstract: Certain aspects of the present disclosure provide techniques for validity of random access channel (RACH) occasions (ROs) in subband full duplex (SBFD) slots. An example method, performed at a user equipment (UE), generally includes receiving a random access channel (RACH) configuration and a subband full duplex (SBFD) configuration, wherein the RACH configuration indicates one or more RACH occasions (ROs) and the SBFD configuration indicates at least one SBFD slot, processing a synchronization signal block (SSB) mapped to at least one first RO of the one or more ROs, determining the at least one first RO in the at least one SBFD slot is valid, based on the RACH configuration, the SBFD configuration, and the mapping, and transmitting a RACH preamble on the at least one first valid RO.
    Type: Application
    Filed: January 27, 2025
    Publication date: August 14, 2025
    Inventors: Abdelrahman Mohamed Ahmed Mohamed IBRAHIM, Muhammad Sayed Khairy ABDELGHAFFAR, Qian ZHANG, Ahmed Attia ABOTABL
  • Publication number: 20250261263
    Abstract: Beam failure recovery (BFR) procedures are described for wireless communications. A base station may send a message to a wireless device during a BFR procedure. The message may comprise one or more BFR configuration parameters and/or reconfigure one or more BFR configuration parameters. The wireless device may stop the BFR procedure, for example, after or in response to receiving the message from the base station. The wireless device may perform a second BFR procedure using one or more of the BFR configuration parameters received in the message.
    Type: Application
    Filed: April 29, 2025
    Publication date: August 14, 2025
    Inventors: Ali Cagatay Cirik, Esmael Hejazi Dinan, Hua Zhou, Alireza Babaei, Hyoungsuk Jeon, Kyungmin Park, Kai Xu
  • Publication number: 20250261283
    Abstract: In emergency or search-and-rescue operations, user devices such as phones may transmit signals that indicate people may be located nearby. The signals can be detected by one or more rover devices, which can explore dangerous terrain for indications of people to be rescued. The user devices can activate an application that conserves battery power while emitting a signal, in some cases in a round robin configuration to further conserve power. The rover devices, or other devices that make contact with the user devices, can collect and manipulate data about the user devices to aid a rescue operation.
    Type: Application
    Filed: April 30, 2025
    Publication date: August 14, 2025
    Inventors: Jim Song, Sarah Lynn O'Brien, Darrin Michael Lea, Henry Vy, Paulyn Ladignon Monasterio, Eric Steven Hill
  • Publication number: 20250261293
    Abstract: This disclosure describes a system including one or more lighting structures, each lighting structure comprising one or more uplights. The system further includes one or more sensors each directed towards a common focal area and a computing device in communication with each of the one or more sensors. The computing device includes one or more processors configured to control the one or more sensors to capture data descriptive of a ball moving above the common focal area. Based on the data, the one or more processors predict a motion characteristic of the ball and compare the motion characteristic to a threshold motion characteristic. In response to the motion characteristic being greater than or equal to the threshold motion characteristic, the one or more processors activate at least one of the one or more uplights.
    Type: Application
    Filed: February 7, 2025
    Publication date: August 14, 2025
    Inventors: Andrew J. Schembs, Alireza Razavi, Jason T. Schutz
  • Publication number: 20250261314
    Abstract: A substrate with built-in electronic components includes an insulator having a first surface and a second surface facing away from the first surface, and a plurality of electronic components built into the insulator, in which each of the electronic components includes a first electrode disposed in a first direction toward the first surface of the insulator and a second electrode disposed in a second direction opposite to the first direction, the electronic components is rectangular in top view from a first surface side, and rectangles of the plurality of electronic components on the first surface side in top view from the first surface side are irregularly disposed.
    Type: Application
    Filed: April 28, 2025
    Publication date: August 14, 2025
    Inventors: Hidehiko SASAKI, Atsushi SAKURAI
  • Publication number: 20250261421
    Abstract: According to one embodiment, a wafer includes a base, a first layer including Alz1Ga1-z1N (0<z1<1), a second layer including Alz2Ga1-z2N (0<z2<z1), a third layer including Alz3Ga1-z3N (0<z3<z2), and a fourth layer. The first layer is between the base and the fourth layer in a first direction. The second layer is between the first layer and the fourth layer in the first direction. The third layer is between the second layer and the fourth layer in the first direction. The fourth layer includes a plurality of first films including Aly1Ga1-y1N (0<y1?1), and a plurality of second films including Aly2Ga1-y2N (0?y2<1, y2<y1).
    Type: Application
    Filed: January 10, 2025
    Publication date: August 14, 2025
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Ryoma KANEKO, Seiya TAKEDA, Shinya NUNOUE, Toshiki HIKOSAKA
  • Publication number: 20250261422
    Abstract: A semiconductor device comprises a contact electrically connected to a source/drain region of a transistor and to a gate region of the transistor. A via is disposed along a side of the contact, wherein the via comprises a conductive material. A dielectric liner layer is disposed around at least a portion of the conductive material. The dielectric liner layer electrically isolates the contact from the conductive material, and the via contacts a bit-line.
    Type: Application
    Filed: February 12, 2024
    Publication date: August 14, 2025
    Inventors: Ruilong Xie, Carl Radens, Lawrence A. Clevenger, Huimei Zhou, Tao Li
  • Publication number: 20250261426
    Abstract: A semiconductor structure including a first backside dielectric, a second backside dielectric, and an etch stop liner sandwiched between the first backside dielectric and the second backside dielectric.
    Type: Application
    Filed: February 14, 2024
    Publication date: August 14, 2025
    Inventors: Sagarika Mukesh, Tao Li, Ruilong Xie, Nicolas Jean Loubet
  • Publication number: 20250261428
    Abstract: A semiconductor device includes an active region extending in a first direction on a substrate, a plurality of channel layers spaced apart from each other in a vertical direction, a gate structure including a gate electrode intersecting the active region and the plurality of channel layers on the substrate and extending around ones of the plurality of channel layers, a gate spacer on side surfaces of the gate electrode, and a gate capping layer on the gate electrode and the gate spacer, a source/drain region on the active region on at least one side of the gate structure and in contact with the plurality of channel layers, and a contact structure on the source/drain region on a side of the gate structure, and electrically connected to the source/drain region. An upper region of the gate capping layer has an end with a rounded upper surface.
    Type: Application
    Filed: October 8, 2024
    Publication date: August 14, 2025
    Inventors: Seonbae Kim, Taeyong Kwon, Daesik Kim, Changhee Kim, Seunghyun Oh, Jimin Yu
  • Publication number: 20250261434
    Abstract: An integrated circuit includes a feedthrough via structure includes a dummy transistor with a dummy gate metal. The dummy transistor is positioned between a first transistor and a second transistor. The dummy gate metal is a different material than the gate metal of the first and second transistors. The feedthrough via structure and electrically connects a backside metal line with a front side metal line. The first and second transistors are positioned between the front side of backside metal lines.
    Type: Application
    Filed: July 19, 2024
    Publication date: August 14, 2025
    Inventors: Chun-Yuan CHEN, Huan-Chieh SU, Chih-Hao WANG
  • Publication number: 20250261441
    Abstract: An integrated circuit device comprises a metal-oxide-semiconductor (MOS) transistor comprising a gate stack formed over a channel region thereof and a bipolar junction transistor (BJT) comprising a layer stack formed over a collector region thereof. Some features of the MOS transistor and the BJT are co-fabricated such that they have common physical characteristics.
    Type: Application
    Filed: March 31, 2025
    Publication date: August 14, 2025
    Inventor: Edward John Coyne
  • Publication number: 20250261444
    Abstract: A semiconductor structure first and second channel regions, an isolation structure, a gate structure, first and second epitaxial features, a dielectric structure, a crystalline hard mask layer, and an amorphous hard mask layer. The isolation structure is disposed between the first channel region and the second channel region. The gate structure interfaces at least three surfaces of the first channel region and at least three surfaces of the second channel region. The first epitaxial feature is adjacent to a sidewall of the first channel region. The second epitaxial feature is adjacent to a sidewall of the second channel region. The dielectric structure is between the first and second channel regions and over the isolation structure. The crystalline hard mask layer is over the dielectric structure. The amorphous hard mask layer is over the dielectric structure and laterally surrounded by the crystalline hard mask layer.
    Type: Application
    Filed: April 22, 2025
    Publication date: August 14, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kun-Yu LEE, Chun-Yao WANG, Chi On CHUI
  • Publication number: 20250261449
    Abstract: Provided are a display panel and a display device. The display panel includes a first display region, a second display region and a first function region. The second display region includes a first signal line extending in the second direction and including a first segment and a second segment that are separated by the first function region. The first display region includes a first display sub-region. The first display sub-region includes a third signal line extending in the second direction and electrically connected to the first segment and the second segment. In the same pixel circuit of the first display sub-region, the second signal line and the third signal line are located on the same side of a fourth signal line.
    Type: Application
    Filed: April 30, 2025
    Publication date: August 14, 2025
    Applicant: Xiamen Tianma Display Technology Co., Ltd.
    Inventor: Guoxing CHEN
  • Publication number: 20250261461
    Abstract: An optical device, such as an imager, successively comprises the following structures: a support in which vias are formed; a first electrode; an active layer capable of absorbing photons and transforming them into electron-hole pairs; a second electrode; a conductive layer connecting the second electrode to one of the vias; and a microlens matrix. The device further includes an encapsulation layer arranged between the microlens matrix and the active layer. The encapsulation layer has a first portion with a first density and a second portion with a second density. The first portion of the encapsulation layer is arranged between the active layer and the second portion of the encapsulation layer. The first density is lower than the second density.
    Type: Application
    Filed: February 7, 2025
    Publication date: August 14, 2025
    Applicant: STMicroelectronics International N.V.
    Inventor: Laurent-Luc CHAPELON
  • Publication number: 20250261462
    Abstract: Image sensors and methods for fabricating image sensors. The method includes forming a first photoresist layer on a planarization layer. The method also includes performing a developing process to form a first hole above a bond pad. The method further includes performing a first dry etching process to form a first trench extending toward the bond pad. The method also includes forming an anti-reflective coating (ARC) layer on the planarization layer and along the first trench. The method further includes forming a second photoresist layer on the ARC layer and inside the first trench. The method also includes performing a developing process to form a second hole in extending from the ARC layer of the first trench to the top side of the image sensor. The method further includes performing a second dry etching process to form a second trench from the first trench to the bond pad.
    Type: Application
    Filed: February 8, 2024
    Publication date: August 14, 2025
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Brian Anthony VAARTSTRA
  • Publication number: 20250261463
    Abstract: Provided are an imaging device and an electronic device configured such that deterioration in imaging performance due to high-angle incident light can be inhibited. The imaging device includes: a semiconductor substrate including a plurality of photoelectric conversion elements; a plurality of color filters that are provided on the semiconductor substrate and face each of the plurality of photoelectric conversion elements; and a partition wall that is provided on the semiconductor substrate and provides separation between one color filter and another color filter adjacent to each other among the plurality of color filters. The partition wall includes a first metal layer, a translucent first partition wall layer that covers a side surface of the first metal layer, and a translucent second partition wall layer located between the first metal layer and the first partition wall layer. A refractive index of the second partition wall layer is larger than a refractive index of the first partition wall layer.
    Type: Application
    Filed: April 29, 2025
    Publication date: August 14, 2025
    Inventor: TETSUYA YAMAGUCHI
  • Publication number: 20250261470
    Abstract: The disclosed semiconductor device package may include a compute chip configured to perform contextual artificial intelligence and machine perception operations. The disclosed semiconductor device package may additionally include a sensor positioned above the compute chip in the semiconductor device package. The disclosed semiconductor device package may also include one or more electrical connections configured to facilitate communication between the compute chip and the sensor, between the compute chip and a printed circuit board, and between the sensor and the printed circuit board. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Application
    Filed: February 7, 2025
    Publication date: August 14, 2025
    Inventors: Rajendra D Pendse, Andrew Samuel Berkovich, Barbara De Salvo, Xinqiao Liu, Clare Joyce Robinson, Tsung-Hsun Tsai, Syed Shakib Sarwar
  • Publication number: 20250261474
    Abstract: Embodiments of the present disclosure provide a solar cell and a photovoltaic module. The solar cell includes: a substrate having a front surface and a rear surface, a first doped polycrystalline silicon layer doped with N-type dopant ions and disposed over the front surface or over the rear surface, and a second doped polycrystalline silicon layer doped with P-type dopant ions and disposed over the rear surface. A surface of the first doped polycrystalline silicon layer away from the substrate has a plurality of first protrusion structures. A surface of the second doped polycrystalline silicon layer away from the substrate has a plurality of second protrusion structures. An average thickness of the first protrusion structures is greater than an average thickness of the second protrusion structures, and a thickness of the first doped polycrystalline silicon layer is not greater than a thickness of the second doped polycrystalline silicon layer.
    Type: Application
    Filed: April 15, 2024
    Publication date: August 14, 2025
    Inventors: Huimin LI, Menglei XU, Jie YANG, Xinyu ZHANG
  • Publication number: 20250261475
    Abstract: The present disclosure provides a back contact solar cell and a manufacturing method therefor, and a photovoltaic module, In one example, a back contact solar cell includes a semiconductor substrate, a transparent conductive layer, and an isolating protective structure. The semiconductor substrate includes a first surface and a second surface opposite to the first surface. The second surface includes N-type regions and P-type regions alternately distributed at intervals, and an isolating region between each of the N-type regions and a corresponding P-type region. The transparent conductive layer covers the second surface. An isolating groove extending through at least the transparent conductive layer is formed on each isolating region The isolating protective structure is formed on a partial region of a groove bottom of the isolating groove. The isolating protective structure includes at least a material of the transparent conductive layer.
    Type: Application
    Filed: September 1, 2023
    Publication date: August 14, 2025
    Inventors: Shenghou ZHOU, Xiyan TANG, Zhaoqing SUN, Xiaoyu DENG, Liang FANG, Feng YE, Xixiang XU
  • Publication number: 20250261476
    Abstract: Discussed is a solar cell including a semiconductor substrate comprising a base region, an emitter region having a conductive type opposite to that of the base region, and a back surface field region having the same conductive type as the base region and a higher doping concentration than the base region, and a first electrode and a second electrode respectively connected to the emitter region and the back surface field region, wherein the base region has a specific resistance of 0.3 ?cm to 2.5 ?cm.
    Type: Application
    Filed: March 11, 2025
    Publication date: August 14, 2025
    Applicant: Trina Solar Co., Ltd.
    Inventors: Jeongkyu KIM, Sunghyun HWANG, Daeyong LEE