Abstract: In accordance with the present invention, a memory system capable of indefinite sequential access to a contiguous address space without stutter is provided. The memory system has a memory array divided into left and right halves, column and row decoders, memory output register banks A and B, and control logic. Upon initial access, the control logic determines whether, in the initial access data to be loaded in register banks A and B cross a row address boundary. If a row address boundary is crossed, data loaded into register bank A corresponds to data in one row in the right half of the memory array, and data in register bank B corresponds to data in the left half of the memory array in the next higher row. Thereafter, register banks A and B are interleaved for loading and output of memory data.

Abstract: In accordance with the present invention, by interleaving two banks of memory output registers, a memory system is provided which allows an indefinite number of sequential accesses to contiguous locations of the memory system, requiring only a reduced access time per output datum after the first initial access, regardless of whether row address boundaries are crossed.

Abstract: An input buffer for coupling TTL logic circuits to CMOS logic circuits, the buffer being used to convert between standard TTL logic signals and CMOS logic signals. The buffer includes a first inverter circuit and a second inverter circuit coupled in a cascade (output of first inverter coupled to the input of the second inverter). The first inverter includes two resistors (Rcc and Rss); the Rcc resistor couples the first inverter to a first reference voltage, which is usually a power supply voltage rail, and Rss couples the first inverter to a second reference voltage. The first inverter also includes a capacitor coupled in parallel with that inverter. Power supply noise is isolated from the first inverter so that the buffer has better immunity from noise than the prior art.

Abstract: A redundant semiconductor memory device is arranged in columns of bit cells addressable in bit segments with a plurality of separate, redundant, columns of bit cells, each separate column being capable of electronic placement at any column position within any bit segment of the memory. Specifically, multiplexer is provided at the output buffers of a memory for multiplexing conventional bit segments with spare columns of bit cells, wherein the spare columns are only activated, that is, selected, when a particular column in the conventional bit segment has been identified to be defective.