Abstract: To supervise a telephone subscriber line (v'2, v'1,) and provide it with adjustable AC and DC termination impedances from the exchange (v1, v2), these are supplied by an impedance synthesis multiple loop split into separate DC and AC loop parts by filters at the output of a sense amplifier in the common loop part and fed (e) through a Herter bridge. The amplifier AC output has however to be limited to avoid saturation by a larger DC signal. It now includes a Miller effect integrator output stage (A2) with a low pass frequency response supplying the DC loop and also feeding back an input stage (A1) so that the latter exhibits a high pass frequency response with a DC free output to drive the AC loop and the consequent ability to supply a larger AC output. Further circuits improve dial pulse detection (LP), reduce external capacitances (C1) and limit power consumption (PG5 and PG6).

Abstract: Each line wire is separately biassed by DC potentials feeding Inputs of the respective line wire driver amplifiers, the first potential (BA) being nearer ground and the second at an equal distance from the negative supply used to power the amplifiers so as to allow a suitable AC swing for the speech and metering signals also feeding the inputs of the amplifiers. The second potential (BB) is obtained from a DC synthesizing loop voltage and to which is added (OA6) the first potential, both potentials being also combined (OA5) to control a switched mode DC/DC converter delivering the negative power supply. In addition to both potentials being filtered with reference to ground, another measure reducing noise relies on AC signals push-pull outputs driving the amplifier inputs, also in push-pull through four resistances.

Abstract: The switching converter (SPC) mainly includes a duty cycle controller (DCC) whose output controls a switch (T1) for transferring energy from an input (VIN) to an output (VOUT). The duty cycle controller (DCC) includes a sawtooth generator (ST) and a pulse generator (NL) whose output signals (STO, NLO) are OR-ed and then compared with an error voltage (VE), derived from the difference between the output voltage (VOUT) and a reference voltage (VREF1), so as to produce an output signal of which the duty cycle varies linearly from a predetermined non-zero value onwards, thus ensuring that during each cycle the switch (T1) is activated for at least a minimum duration.