Abstract: A frequency synthesizer or a circuit for deleting cycles from a wave source includes a dual modulus counter responsive to a reference frequency source of the synthesizer or waves of the source. The dual modulus counter selectively decreases the number of cycles of the source by the factors K.sub.2 and (K.sub.2 +1). A frequency divider divides the frequency of the source by a third factor L to derive an output wave. The dual modulus counter is activated so it divides by K.sub.2 +1, whereby the dual modulus counter derives an output signal having a frequency F.sub.0 =F.sub.in /K.sub.2 (1-1/L), where F.sub.in equals the frequency of the source, L is an integer and K.sub.2 is an integer greater than L.