Abstract: A level-‘n’ cache and method are disclosed. The level-‘n’ cache method comprises: in response to a data access request identifying an address of a data block to be accessed, interrogating an address cache of the level-‘n’ cache arranged to store address portions for a sub-set of data blocks stored in a main cache of the level-‘n’ cache to determine whether a cache hit occurs within the address cache for the address. In this way, providing the address cache which is separate from the main cache, with the address cache storing address portions relating to data blocks stored in the main cache, the amount of data required to be stored in the address cache is reduced, and decouples the size of the address cache from that of the main cache which enables the address cache to be sized independent of the size of the data blocks stored in the main cache.

Abstract: A graphics processing system includes a graphics processor 1 that renders output frames that are written to a frame buffer in a memory 2 for display on a display 7. Comparison and control hardware 5 of the graphics processing system operates to compare successive output frames that are being generated for display, and then controls one or more aspects of the way in which the display of the output frames generated by the graphics processor 1 is carried out. In one preferred embodiment, the rate at which the display device 7 is updated (refreshed) from the frame buffer is controlled on the basis of the output frame comparisons. In another preferred embodiment, the format used when storing the output frames in the frame buffer is selected on the basis of the output frame comparisons.