Abstract: A semiconductor device includes a semiconductor die having a vertical transistor device with a source electrode, a drain electrode and a gate electrode, the semiconductor die having a first surface and a second surface opposing the first surface. A first metallization structure is located on the first surface and includes at least one source pad coupled to the source electrode, at least one drain pad coupled to the drain electrode and at least one gate pad coupled to the gate electrode, A second metallization structure is electrically insulated from the semiconductor die by the electrically insulating layer.

Abstract: A semiconductor device includes: a carrier including an electronic circuit; a plurality of semiconductor chip packages mounted on the carrier, each of the chip packages including an encapsulation encapsulating the semiconductor chip, a plurality of contact structures electrically connecting the semiconductor chip with the electronic circuit, and at least one cooling structure protruding from the encapsulation; and a cooling element thermally conductively connected to at least one cooling structure of each of at least two of the plurality of semiconductor chip packages.

Abstract: A semiconductor device includes: a carrier including an electronic circuit; a plurality of semiconductor chip packages mounted on the carrier, each of the chip packages including an encapsulation encapsulating the semiconductor chip, a plurality of contact structures electrically connecting the semiconductor chip with the electronic circuit, and at least one cooling structure protruding from the encapsulation; and a cooling element thermally conductively connected to at least one cooling structure of each of at least two of the plurality of semiconductor chip packages.

Abstract: A chip package is provided. The chip package includes a semiconductor chip having on a front side a first connecting pad and a second connecting pad, a carrier having a pad contact area and a recess, encapsulation material encapsulating the conductor chip, a first external connection that is free from or extends out of the encapsulation material, an electrically conductive clip, and a contact structure. The semiconductor chip is arranged with its front side facing the carrier with the first connecting pad over the recess and with the second connecting pad contacting the pad contact area. The clip is arranged over a back side of the semiconductor chip covering the semiconductor chip where it extends over the recess. The electrically conductive contact structure electrically conductively connects the first connecting pad with the first external connection.

Abstract: In some embodiments, a semiconductor device comprises a semiconductor die comprising a vertical transistor device having a source electrode, a drain electrode and a gate electrode, the semiconductor die having a first surface and a second surface opposing the first surface. A first metallization structure is located on the first surface and comprises at least one source pad coupled to the source electrode, at least one drain pad coupled to the drain electrode and at least one gate pad coupled to the gate electrode. A second metallization structure is located on the second surface and comprises a conductive structure and an electrically insulating layer and forms an outermost surface of the semiconductor device. The outermost surface of the second metallization structure is electrically insulated from the semiconductor die by the electrically insulating layer.

Abstract: A multiphase inverter apparatus includes: an insulating substrate; at least one low voltage bus and at least one high voltage bus on a first surface of the insulating substrate; a plurality of half-bridge circuits, each half-bridge circuit being electrically coupled between a respective one of the at least one low voltage bus and a respective one of the at least one high voltage bus; and a phase output lead for each half-bridge circuit. For each half bridge circuit, the phase output lead is arranged on and electrically coupled to at least one packaged low side switch and at least one packaged high side switch of the half bridge circuit such that each packaged low side switch and each packaged high side switch is arranged vertically between the phase output lead and the first surface of the insulating substrate.

Abstract: A multiphase inverter apparatus includes an insulating substrate, a plurality of half bridge circuits and a phase output lead for each half bridge circuit. The substrate includes a conductive redistribution structure on a first surface and having at least one low voltage bus and at least one high voltage bus. Each half-bridge circuit is electrically coupled between a low voltage bus and a high voltage bus and includes: a packaged low side switch; a packaged high side switch; and a phase output electrically coupled with the respective phase output lead. The packaged low side and high side switches are arranged on the first surface of the substrate. The phase output lead is arranged on and electrically coupled to the packaged low side and high side switches such that the low side and high side switches are arranged vertically between the phase output lead and the first surface of the substrate.

Abstract: In an embodiment, a circuit arrangement is provided that includes a half-bridge circuit and a substrate having a major surface. The half-bridge circuit includes a high voltage node, a low voltage node and an output node. A high side switch and a low side switch are coupled in series and provide a pair and n pairs are coupled in parallel between the high voltage node and the low voltage node, n being an integer greater than or equal to 2. The output node is provided by an output connector on the major surface of the substrate. The output connector has an axis perpendicular to the major surface of the substrate and the n pairs are arranged on the major surface of the substrate and are uniformly distributed around the axis of the output connector.

Abstract: A multiphase inverter apparatus includes an insulating substrate, a plurality of half bridge circuits and a phase output lead for each half bridge circuit. The substrate includes a conductive redistribution structure on a first surface and having at least one low voltage bus and at least one high voltage bus. Each half-bridge circuit is electrically coupled between a low voltage bus and a high voltage bus and includes: a packaged low side switch; a packaged high side switch; and a phase output electrically coupled with the respective phase output lead. The packaged low side and high side switches are arranged on the first surface of the substrate. The phase output lead is arranged on and electrically coupled to the packaged low side and high side switches such that the low side and high side switches are arranged vertically between the phase output lead and the first surface of the substrate.

Abstract: A chip package is provided. The chip package includes a semiconductor chip having on a front side a first connecting pad and a second connecting pad, a carrier having a pad contact area and a recess, encapsulation material encapsulating the conductor chip, a first external connection that is free from or extends out of the encapsulation material, an electrically conductive clip, and a contact structure. The semiconductor chip is arranged with its front side facing the carrier with the first connecting pad over the recess and with the second connecting pad contacting the pad contact area. The clip is arranged over a back side of the semiconductor chip covering the semiconductor chip where it extends over the recess. The electrically conductive contact structure electrically conductively connects the first connecting pad with the first external connection.

Abstract: In an embodiment, a circuit arrangement is provided that includes a half-bridge circuit and a substrate having a major surface. The half-bridge circuit includes a high voltage node, a low voltage node and an output node. A high side switch and a low side switch are coupled in series and provide a pair and n pairs are coupled in parallel between the high voltage node and the low voltage node, n being an integer greater than or equal to 2. The output node is provided by an output connector on the major surface of the substrate. The output connector has an axis perpendicular to the major surface of the substrate and the n pairs are arranged on the major surface of the substrate and are uniformly distributed around the axis of the output connector.

Abstract: A power electronic device includes an Insulated Metal Substrate Printed Circuit Board (IMS PCB) and a power semiconductor device package. The power semiconductor device package includes a lead frame configured to electrically and mechanically couple the power semiconductor device package to the IMS PCB. The lead frame has a rigid configuration and is made of a lead frame material having a first thermal expansion coefficient. The IMS PCB includes an insulated metal substrate made of a substrate material having a second thermal expansion coefficient within a range of 60% to 140% of the first thermal expansion coefficient.

Abstract: A power electronic device includes an Insulated Metal Substrate Printed Circuit Board (IMS PCB) and a power semiconductor device package. The power semiconductor device package includes a lead frame configured to electrically and mechanically couple the power semiconductor device package to the IMS PCB. The lead frame has a rigid configuration and is made of a lead frame material having a first thermal expansion coefficient. The IMS PCB includes an insulated metal substrate made of a substrate material having a second thermal expansion coefficient within a range of 60% to 140% of the first thermal expansion coefficient.

Abstract: A device including a first semiconductor package that includes a semiconductor chip, an encapsulation material at least partly covering the semiconductor chip, and a contact element electrically coupled to the semiconductor chip and protruding out of the encapsulation material. In addition, the device includes a printed circuit board (PCB), wherein the first semiconductor package is mounted on the PCB and the contact element of the first semiconductor package is electrically coupled to the PCB. The device further includes a first metal workpiece mounted on the printed circuit board and electrically coupled to the contact element of the first semiconductor package.

Abstract: A device including a first semiconductor package that includes a semiconductor chip, an encapsulation material at least partly covering the semiconductor chip, and a contact element electrically coupled to the semiconductor chip and protruding out of the encapsulation material. In addition, the device includes a printed circuit board (PCB), wherein the first semiconductor package is mounted on the PCB and the contact element of the first semiconductor package is electrically coupled to the PCB. The device further includes a first metal workpiece mounted on the printed circuit board and electrically coupled to the contact element of the first semiconductor package.

Abstract: A sump pump control system for monitoring and driving AC pumps that are supplied by directly either by AC utility power, or converted DC battery power. AC power is continuously monitored and the control automatically switches to DC battery supply in the case of power failure. DC battery power is converted to AC power. The control is equipped with unique pump switching circuitry allowing the pumps to be configured in parallel or staggered positions. Both pumps automatically alternate to prevent damage to pumps from humidity and corrosion that can result from remaining idle. Each pump has its own float switch to control operation. A third float switch controls both pumps in case of failure of either pump or float switch. Multiple visual and audio signals are included, displaying present power and pump conditions as well as alerting to any pump malfunction.

Abstract: This unit is intermittent duty, small, and light weight. Use of a thyristor(s) control reduces the unit's energy consumption through reduced AC input voltage while still producing sufficient demagnetizing power and effective demagnetizing results. This principle may be applied to ANY and ALL sizes of demagnetizing coils. With the burst control we can achieve same demagnetizing power and reduce overall power consumption of the demagnetizing coil(s) reducing size and weight of the coil(s). For this intermittent duty coil(s) the power consumption is reduced by over 40% and heating rate reduced which allows approx. 40% longer continuous running time.

Abstract: A sump pump control system for monitoring and driving AC pumps that are supplied by directly either by AC utility power, or converted DC battery power. AC power is continuously monitored and the control automatically switches to DC battery supply in the case of power failure. DC battery power is converted to AC power. The control is equipped with unique pump switching circuitry allowing the pumps to be configured in parallel or staggered positions. Both pumps automatically alternate to prevent damage to pumps from humidity and corrosion that can result from remaining idle. Each pump has its own float switch to control operation. A third float switch controls both pumps in case of failure of either pump or float switch. Multiple visual and audio signals are included, displaying present power and pump conditions as well as alerting to any pump malfunction.