Abstract: Reducing CMP wafer contamination by in-situ clean is disclosed herein. The invention can be employed in a method in which a conductive layer is formed on a surface of a semiconductor wafer. After a portion of the conductive layer is removed, an acidic solution is directly or indirectly applied to the semiconductor wafer. Then the semiconductor wafer is engaged with a polishing pad as the acidic solution is applied directly or indirectly to the semiconductor wafer. In one embodiment, the portion of the conductive layer is removed by a CMP tool, and the semiconductor wafer is engaged with the polishing pad before the semiconductor is removed from the CMP tool.

Abstract: A method for improving the reliability of integrated circuits. In one embodiment, the method includes forming a dielectric layer on a semiconductor wafer. A trench is then formed in the dielectric. Thereafter, a conductive interconnect is formed within the trench, wherein the conductive interconnect comprises copper. The conductive interconnect is then etched using an acidic solution. Lastly, a conductive layer is formed on an exposed surface of the etched conductive interconnect.