Abstract: A digital switching network for providing simultaneous connections among user processors of processor-based communications equipment. The user processors act as originators and destinations of data communications packets. Packet data connections are through node controllers, which communicate with gateways, which are connected to a switching network via packet links. Control messages are communicated between node controllers, gateways, and an interchange control subsystem via various control message links. All control message processing and packet data transmissions are synchronized with a packet frame synchronization signal, and processing tasks performed by each of the network subsystems are pipelined so that they occur simultaneously. Service requests are queued in a central queue in the interchange control system. The synchronization and queueing simplify the control messages that are required to set up and release the connections.

Abstract: A message transport network (10) is provided for high speed switching between processing elements (72, 80). Clusters of low speed processing elements (72) may be connected to the message transport network (10) through a transport node controller (78). The transport node controller (78) and the high speed processors (80) are connected to the gateways (82). A pair of gateways (82) may be connected through a transport interchange node (106) to allow communication between processors (72, 80) associated with the gateways (82). A transport interchange supervisor (98) maintains a record of the status of each gateway (82) and generates commands to form connection between gateways (82) in the transport interchange node (106). A maintenance controller (102) and system maintenance processor (76) oversee the validity of the data being passed through the system on paths independent of the data transfer paths.

Abstract: An apparatus is provided for reducing customer transaction time in an automated teller machine (ATM) having various peripheral devices associated therewith. Each peripheral device associated with the ATM; e.g., a card handler mechanism, a printer mechanism, one or more cash dispenser mechanisms, and a depository mechanism, include a dedicated processor and memory for controlling the operation of the peripheral device connected thereto. The ATM also includes a peripheral control unit connected to the various subsystem controllers and to an ATM control unit for receiving generated transaction sequence event messages and in response thereto concurrently processing the messages to initiate simultaneous real-time operation of the various peripheral devices. For example, the concurrent processing of transaction sequence event messages allows completion of the card read activity, entry of a customer PIN and printing of the customer receipt header to take place simultaneously.