Abstract: A method to generate an erasure locator polynomial in an error-and-erasure decode. The method generally includes the steps of (A) storing current values in multiple registers at a current moment, (B) generating first values by multiplying each current value by a respective one of multiple constants, (C) generating second values by gating at least all but one of the first values with a current one of multiple erasure values of an erasure position vector, (D) generating next values by combining each one of the second values with a corresponding one of the first values, (E) loading the next values into the registers in place of the current values at a next moment and (F) generating an output signal carrying the current values at a last moment such that the current values form the coefficients of the erasure locator polynomial.

Abstract: The present invention is a configurable binary BCH encoder having a variable number of errors. The encoder may implement a universal multipole block which may be configured for receiving an error number input, which may include a maximum error number limit for the encoder, and for calculating a plurality of error coefficients based on the error number input. The encoder may be further configured for receiving a plurality of information bits of an information word. The encoder may be further configured for transmitting/outputting a first (ex.—unmodified) subset of the information bits as an encoder output. The encoder may be further configured for calculating a plurality of parity bits based on a second subset of the information bits and the error coefficients. The encoder may be further configured for transmitting/outputting the calculated parity bits as part of the encoder output.

Abstract: A method and apparatus for calculating ramptime propagation for integrated circuit layout patterns having pins interconnected in an oriented graph in one or more closed loops is described. Ramptime values are calculated for a first set of the pins, which are not connected to a closed loop while leaving a second set of the pins with unknown ramptime values. One or more closed loops are identified by backtracking from the pins in the second set with unknown ramptime values. A ramptime value for each pin in the one or more closed loops is calculated iteratively.

Abstract: A method of configurable decoding is disclosed. The method generally includes the steps of (A) receiving a variable value in a configuration signal, (B) calculating a plurality of first syndromes corresponding to a particular codeword of a plurality of codewords received in an input signal, the particular codeword having a plurality of information symbols and a plurality of parity symbols coded such that up to a fixed value of a plurality of errors in the particular codeword are correctable, the fixed value being greater than the variable value, (C) transforming the first syndromes into a plurality of second syndromes such that no greater than the variable value of the errors in the particular codeword are correctable and (D) generating an intermediate signal carrying the second syndromes.

Abstract: The present disclosure is directed to a method of selecting cells in an integrated circuit for logic restructuring of an original design. The original design includes a set of parameters. The method includes forming a restructuring set that will include the selected cells for logic restructuring, and a candidate set. The restructuring set includes restructuring cells with an initial cell. The restructuring set is adapted to accept additional cells identified as restructuring cells. The candidate set is adapted to include candidate cells, where each candidate cell in the candidate set is connected to at least one of the restructuring cells in the restructuring set. The candidate set is adapted to remove candidate cells from the candidate set. The restructuring set is adapted to accept selected removed candidate cells as identified restructuring cells if a corresponding parameter is included in the set of parameters.

Abstract: The present disclosure is directed to a method and apparatus for dividing an integrated circuit design field into a plurality of congestion rectangles having user-selectable sizes. A routing congestion value is estimated for each congestion rectangle prior to routing interconnections within the design field. The congestion values are stored in machine-readable memory and are updated in response to wire changes within the design field.

Abstract: The present invention provides a new approach and algorithm to optimize various design parameters in global routing. According to an exemplary aspect of the present invention, marked trees are first preprocessed. For every vertex incident to leaves, one may go through the list of its leaves, and if two leaves have the same mark one may leave only one of them. After that whether homeomorphism exists may be determined. The reason behind selecting such homeomorphic pairs is as follows: adding or removing a vertex of degree 2 as well as adding or removing a new leaf (variable) does not significantly modify routing (in this case all routing transformations are in essence splitting and merging routing trees). After the selection of applicable transformations, one may apply them to optimize design parameters.

Abstract: An improvement to a key equation solver block for a BCH decoder, where the key equation solver block having a number of multiplier units specified by X, where: t*(7*t?1)/(codeword_len?3)?X<(t+1), where t is a number of transmission errors for the key equation solver block to correct, and codeword_len is a length of a transmitted codeword to be decoded by the BCH decoder.

Abstract: Buffers are inserted into an integrated circuit chip design using a table that identifies buffer types based on buffer height, input capacitance, output capacitance and ramptime. A buffer routing tree is created having root, internal and leaf vertices. For each internal vertex, the initial circuit parameters are compared to circuit parameters associated with buffers identified in the table to identify whether a buffer identified in the table can be inserted to the respective internal vertex. If it can, an optimal insertable buffer is selected from the table and inserted to a selected internal vertex based at least in part on the comparison results. Also described is a computer process of creating the buffer type table.

Abstract: A method for calculating ramptime propagation for integrated circuit layout patterns having pins interconnected in an oriented graph in one or more closed loops is described. Ramptime values are calculated for a first set of the pins, which are not connected to a closed loop while leaving a second set of the pins with unknown ramptime values. One or more closed loops are identified by backtracking from the pins in the second set with unknown ramptime values. A ramptime value for each pin in the one or more closed loops is calculated iteratively.

Abstract: The present disclosure is directed to a method of selecting cells in an integrated circuit for logic restructuring of an original design. The original design includes a set of parameters. The method includes forming a restructuring set that will include the selected cells for logic restructuring, and a candidate set. The restructuring set includes restructuring cells with an initial cell. The restructuring set is adapted to accept additional cells identified as restructuring cells. The candidate set is adapted to include candidate cells, where each candidate cell in the candidate set is connected to at least one of the restructuring cells in the restructuring set. The candidate set is adapted to remove candidate cells from the candidate set. The restructuring set is adapted to accept selected removed candidate cells as identified restructuring cells if a corresponding parameter is included in the set of parameters.

Abstract: An iterative process assigns nodes of a new logical tree to positions in a space that was previously assigned to an old logical tree equivalent to the new logical tree. A path in the new tree is identified for an essential node of the new tree. Coordinates of a position in the space are identified for an old tree node that is equivalent to a son of the essential node. Coordinates are iteratively identified for each node in the new tree path using a free space algorithm and based on the nodes of the new tree path and the coordinates identified for the old tree node that is equivalent to the son of the essential node. If all sons of the essential node are leaves of the new tree, the old tree node is a leaf node equivalent to the son. Otherwise, the old tree node is identified in a prior iteration.

Abstract: An IC layout containing megacells placed in violation of design rules is corrected to remove design rule violations while maintaining the original placement as near as practical. The sizes of at least some of the megacells are inflated. The megacells are placed and moved in a footprint of the circuit in a manner to reduce placement complexity. The placement of the megacells is permuted to reduce placement complexity. Additional movements are be applied to the permuted placement to further reduce placement complexity.

Abstract: The present invention is directed to a method and apparatus to find an optimal unification substitution for formulas in a technology library. In an exemplary aspect of the present invention, a method for finding an optimal unification substitution for formulas in a technology library during integrated circuit design may include the following steps: (a) receiving input including a list L of pairs of formulas in standard form, a set S of substitutions for variables, a right part e(x1, . . . , xp) of an identity, and an information I={t, h, r, a, p} on best application; (b) when the list L is not empty, extracting and removing first pair (ƒ?(A?1, . . . , A?n?), g?(B?1, . . . , B?m?)) from the list L; (c) removing head inverters and buffers from formulas ƒ?(A?1, . . . , A?n?) and g?(B?1, . . . , B?m?)) and obtaining a pair (ƒ(A1, . . . , An), g(B1, . . . , Bm)); (d) when the ƒ is a commutative operation but neither a variable nor constant, and when heads of the formulas ƒ(A1, . . . , An) and g(B1, . . .

Abstract: The present invention is directed to a system and method of finding Boolean symmetries. In aspects of the present invention, a method, system and computer-readable medium constructs a symmetry tree for any Boolean function. A data structure which describes groups of commutative variables of a Boolean function is called a symmetry tree of the Boolean function.

Abstract: The present invention is directed to a system and method for providing multidirectional routing. The present invention may provide an arbitrary number of routing layers and an arbitrary direction on each of those layers to provide a smaller die size and to reduce power consumption by providing more flexibility for net routing directions.

Abstract: A process of optimizing setup and hold time violations comprising resynthesis of data and clock logics coupled to pins of the integrated circuit to optimize setup time violations, and resynthesizing data and clock logics coupled to pins of the integrated circuit to optimize hold time violations. Optimization of setup time violations is performed by resynthesis of the clock logics of each pin having a setup time violation to optimize the setup time violations, then resynthesis of the data logics of each pin having a setup time violation to optimize the setup time violations, and then resynthesis of the clock logics of each pin having a setup time violation to optimize the setup time violations. The hold time violations are then optimized by resynthesizing the data logics to optimize the hold time violations, and then resynthesizing the clock logics to optimize the hold time violations.

Abstract: The present invention is directed to a system and method of finding Boolean symmetries. In aspects of the present invention, a method, system and computer-readable medium constructs a symmetry tree for any Boolean function. A data structure which describes groups of commutative variables of a Boolean function is called a symmetry tree of the Boolean function.

Abstract: A process of optimizing setup and hold time violations comprising resynthesis of data and clock logics coupled to pins of the integrated circuit to optimize setup time violations, and resynthesizing data and clock logics coupled to pins of the integrated circuit to optimize hold time violations. Optimization of setup time violations is performed by resynthesis of the clock logics of each pin having a setup time violation to optimize the setup time violations, then resynthesis of the data logics of each pin having a setup time violation to optimize the setup time violations, and then resynthesis of the clock logics of each pin having a setup time violation to optimize the setup time violations. The hold time violations are then optimized by resynthesizing the data logics to optimize the hold time violations, and then resynthesizing the clock logics to optimize the hold time violations.

Abstract: A method of testing a floor plan for an integrated circuit prior to resynthesis includes attempting to construct a least-penalty path connecting pins of each long distance pin pair in the floor plan to determine whether the floor plan has an unreachable pin; and if the least-penalty path is constructed, then attempting to construct a least-penalty path connecting pins of each long distance pin pair in the floor plan to determine whether the floor plan has a bottleneck.