Abstract: An apparatus having a memory and a controller is disclosed. The memory is configured to store a codeword. The controller is configured to (i) determine one or more least-reliable bit positions in a soft-decision version of the codeword in response to failing to decode a hard-decision version of the codeword, (ii) generate a trial codeword by selecting at random a respective value in one or more trial positions among the least-reliable bit positions in the hard-decision codeword and (iii) perform a hard-decision decoding of the trial codeword.

Abstract: An apparatus having a memory and a controller is disclosed. The memory is configured to store a codeword. The controller is configured to (i) determine one or more least-reliable bit positions in a soft-decision version of the codeword in response to failing to decode a hard-decision version of the codeword, (ii) generate a trial codeword by selecting at random a respective value in one or more trial positions among the least-reliable bit positions in the hard-decision codeword and (iii) perform a hard-decision decoding of the trial codeword.

Abstract: A syndrome calculator receives an input codeword and calculates a first set of syndromes. A syndrome transform receives the first set of syndromes having and determines a second set of syndromes. The second set of syndromes is based on the first set of syndromes. The second set of syndromes has number of syndromes that is less than the number of syndromes in the first set of syndromes. A key equation solver receives the second set of syndromes and produces an indication of zero or more error locations and an indication of zero or more error values.

Abstract: A fixed length Reed-Solomon encoder is configured to produce a first fixed number of redundant symbols. The fixed length Reed-Solomon encoder is configured with an encoding polynomial that is fixed. A symbol preprocessor maps each input data symbol to a transformed input data symbol. A symbol postprocessor maps a second fixed number of redundant symbols output from the fixed length Reed-Solomon encoder to a set of redundant symbols. The second fixed number of redundant symbols is less than the first fixed number of redundant symbols.

Abstract: A syndrome calculator receives an input codeword and calculates a first set of syndromes. A syndrome transform receives the first set of syndromes having and determines a second set of syndromes. The second set of syndromes is based on the first set of syndromes. The second set of syndromes has number of syndromes that is less than the number of syndromes in the first set of syndromes. A key equation solver receives the second set of syndromes and produces an indication of zero or more error locations and an indication of zero or more error values.

Abstract: A fixed length Reed-Solomon encoder is configured to produce a first fixed number of redundant symbols. The fixed length Reed-Solomon encoder is configured with an encoding polynomial that is fixed. A symbol preprocessor maps each input data symbol to a transformed input data symbol. A symbol postprocessor maps a second fixed number of redundant symbols output from the fixed length Reed-Solomon encoder to a set of redundant symbols. The second fixed number of redundant symbols is less than the first fixed number of redundant symbols.

Abstract: A method and apparatus for calculating ramptime propagation for integrated circuit layout patterns having pins interconnected in an oriented graph in one or more closed loops is described. Ramptime values are calculated for a first set of the pins, which are not connected to a closed loop while leaving a second set of the pins with unknown ramptime values. One or more closed loops are identified by backtracking from the pins in the second set with unknown ramptime values. A ramptime value for each pin in the one or more closed loops is calculated iteratively.

Abstract: The present disclosure is directed to a method and apparatus for dividing an integrated circuit design field into a plurality of congestion rectangles having user-selectable sizes. A routing congestion value is estimated for each congestion rectangle prior to routing interconnections within the design field. The congestion values are stored in machine-readable memory and are updated in response to wire changes within the design field.

Abstract: The present disclosure is directed to a method of selecting cells in an integrated circuit for logic restructuring of an original design. The original design includes a set of parameters. The method includes forming a restructuring set that will include the selected cells for logic restructuring, and a candidate set. The restructuring set includes restructuring cells with an initial cell. The restructuring set is adapted to accept additional cells identified as restructuring cells. The candidate set is adapted to include candidate cells, where each candidate cell in the candidate set is connected to at least one of the restructuring cells in the restructuring set. The candidate set is adapted to remove candidate cells from the candidate set. The restructuring set is adapted to accept selected removed candidate cells as identified restructuring cells if a corresponding parameter is included in the set of parameters.

Abstract: A method for calculating ramptime propagation for integrated circuit layout patterns having pins interconnected in an oriented graph in one or more closed loops is described. Ramptime values are calculated for a first set of the pins, which are not connected to a closed loop while leaving a second set of the pins with unknown ramptime values. One or more closed loops are identified by backtracking from the pins in the second set with unknown ramptime values. A ramptime value for each pin in the one or more closed loops is calculated iteratively.

Abstract: Buffers are inserted into an integrated circuit chip design using a table that identifies buffer types based on buffer height, input capacitance, output capacitance and ramptime. A buffer routing tree is created having root, internal and leaf vertices. For each internal vertex, the initial circuit parameters are compared to circuit parameters associated with buffers identified in the table to identify whether a buffer identified in the table can be inserted to the respective internal vertex. If it can, an optimal insertable buffer is selected from the table and inserted to a selected internal vertex based at least in part on the comparison results. Also described is a computer process of creating the buffer type table.

Abstract: The present disclosure is directed to a method of selecting cells in an integrated circuit for logic restructuring of an original design. The original design includes a set of parameters. The method includes forming a restructuring set that will include the selected cells for logic restructuring, and a candidate set. The restructuring set includes restructuring cells with an initial cell. The restructuring set is adapted to accept additional cells identified as restructuring cells. The candidate set is adapted to include candidate cells, where each candidate cell in the candidate set is connected to at least one of the restructuring cells in the restructuring set. The candidate set is adapted to remove candidate cells from the candidate set. The restructuring set is adapted to accept selected removed candidate cells as identified restructuring cells if a corresponding parameter is included in the set of parameters.

Abstract: An iterative process assigns nodes of a new logical tree to positions in a space that was previously assigned to an old logical tree equivalent to the new logical tree. A path in the new tree is identified for an essential node of the new tree. Coordinates of a position in the space are identified for an old tree node that is equivalent to a son of the essential node. Coordinates are iteratively identified for each node in the new tree path using a free space algorithm and based on the nodes of the new tree path and the coordinates identified for the old tree node that is equivalent to the son of the essential node. If all sons of the essential node are leaves of the new tree, the old tree node is a leaf node equivalent to the son. Otherwise, the old tree node is identified in a prior iteration.

Abstract: The present invention provides a new approach and algorithm to optimize various design parameters in global routing. According to an exemplary aspect of the present invention, marked trees are first preprocessed. For every vertex incident to leaves, one may go through the list of its leaves, and if two leaves have the same mark one may leave only one of them. After that whether homeomorphism exists may be determined. The reason behind selecting such homeomorphic pairs is as follows: adding or removing a vertex of degree 2 as well as adding or removing a new leaf (variable) does not significantly modify routing (in this case all routing transformations are in essence splitting and merging routing trees). After the selection of applicable transformations, one may apply them to optimize design parameters.

Abstract: An IC layout containing megacells placed in violation of design rules is corrected to remove design rule violations while maintaining the original placement as near as practical. The sizes of at least some of the megacells are inflated. The megacells are placed and moved in a footprint of the circuit in a manner to reduce placement complexity. The placement of the megacells is permuted to reduce placement complexity. Additional movements are be applied to the permuted placement to further reduce placement complexity.

Abstract: The present invention is directed to a method and apparatus to find an optimal unification substitution for formulas in a technology library. In an exemplary aspect of the present invention, a method for finding an optimal unification substitution for formulas in a technology library during integrated circuit design may include the following steps: (a) receiving input including a list L of pairs of formulas in standard form, a set S of substitutions for variables, a right part e(x1, . . . , xp) of an identity, and an information I={t, h, r, a, p} on best application; (b) when the list L is not empty, extracting and removing first pair (f?(A?1, . . . , A?n?), g?(B?1, . . . , B?m?)) from the list L; (c) removing head inverters and buffers from formulas f?(A?1, . . . , A?n?) and g?(B?1, . . . , B?m?)) and obtaining a pair (f(A1, . . . , An), g(B1, . . . , Bm)); (d) when the ƒ is a commutative operation but neither a variable nor constant, and when heads of the formulas f(A1, . . . , An) and g(B1, . . .