Abstract: A manufacturing method of a flash memory comprising forming a patterned first dielectric layer, forming a patterned first conductive layer and a patterned hard mask layer on a substrate. Next, forming a conformal second conductive layer on the substrate, and etching back the second conductive layer by using the hard mask layer as a etching stop layer to form a conductive spacer on both of the sidewalls of the first conductive layer. Thereafter, removing the hard mask layer, and forming a second dielectric layer and a third conductive layer on the substrate. Finally, a stacked gate structure is constructed by the third conductive layer, the second dielectric layer, the first conductive layer, the conductive spacer and the first dielectric layer, in which a floating gate of the stacked gate structure is constructed by a remainer portion of the first conductive layer and the conductive spacer. And a source/drain region is formed in both sides of the stacked gate structure.

Abstract: A manufacturing method of a flash memory comprising forming a patterned first dielectric layer, forming a patterned first conductive layer and a patterned hard mask layer on a substrate. Next, forming a conformal second conductive layer on the substrate, and etching back the second conductive layer by using the hard mask layer as a etching stop layer to form a conductive spacer on both of the sidewalls of the first conductive layer. Thereafter, removing the hard mask layer, and forming a second dielectric layer and a third conductive layer on the substrate. Finally, a stacked gate structure is constructed by the third conductive layer, the second dielectric layer, the first conductive layer, the conductive spacer and the first dielectric layer, in which a floating gate of the stacked gate structure is constructed by a remainer portion of the first conductive layer and the conductive spacer. And a source/drain region is formed in both sides of the stacked gate structure.