Patents by Inventor Elzbieta A. Kolawa

Elzbieta A. Kolawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7514964
    Abstract: An universal and programmable logic gate based on G4-FET technology is disclosed, leading to the design of more efficient logic circuits. A new full adder design based on the G4-FET is also presented. The G4-FET can also function as a unique router device offering coplanar crossing of signal paths that are isolated and perpendicular to one another. This has the potential of overcoming major limitations in VLSI design where complex interconnection schemes have become increasingly problematic.
    Type: Grant
    Filed: March 15, 2006
    Date of Patent: April 7, 2009
    Assignee: California Institute of Technology
    Inventors: Amir Fijany, Farrokh Vatan, Kerem Akarvardar, Benjamin Blalock, Suheng Chen, Sorin Cristoloveanu, Elzbieta Kolawa, Mohammad M. Mojarradi, Nikzad Toomarian
  • Publication number: 20070008013
    Abstract: An universal and programmable logic gate based on G4-FET technology is disclosed, leading to the design of more efficient logic circuits. A new full adder design based on the G4-FET is also presented. The G4-FET can also function as a unique router device offering coplanar crossing of signal paths that are isolated and perpendicular to one another. This has the potential of overcoming major limitations in VLSI design where complex interconnection schemes have become increasingly problematic.
    Type: Application
    Filed: March 15, 2006
    Publication date: January 11, 2007
    Inventors: Amir Fijany, Farrokh Vatan, Kerem Akarvardar, Benjamin Blalock, Suheng Chen, Sorin Cristoloveanu, Elzbieta Kolawa, Mohammad Mojarradi, Nikzad Toomarian
  • Publication number: 20040197983
    Abstract: Electrically active devices are formed using a special conducting material of the form Tm-Ox mixed with SiO2 where the materials are immiscible. The immiscible materials are forced together by using high energy process to form an amorphous phase of the two materials. The amorphous combination of the two materials is electrically conducting but forms an effective barrier.
    Type: Application
    Filed: April 20, 2004
    Publication date: October 7, 2004
    Applicant: California Institute of Technology, a corporation
    Inventors: Pierre Giauque, Marc Nicolet, Stefan M. Gasser, Elzbieta A. Kolawa, Hilary Cherry
  • Patent number: 6723436
    Abstract: Electrically active devices are formed using a special conducting material of the form Tm—Ox mixed with SiO2 where the materials are immiscible. The immiscible materials are forced together by using high energy process to form an amorphous phase of the two materials. The amorphous combination of the two materials is electrically conducting but forms an effective barrier.
    Type: Grant
    Filed: March 22, 2000
    Date of Patent: April 20, 2004
    Assignee: California Institute of Technology
    Inventors: Pierre Giauque, Marc Nicolet, Stefan M. Gasser, Elzbieta A. Kolawa, Hillary Cherry
  • Patent number: 6114256
    Abstract: An adherent and metallurgically stable metallization system for diamond is presented. The big improvement in metallurgical stability is attributed to the use of a ternary, amorphous Ti--Si--N diffusion barrier. No diffusion between the layers and no delamination of the metallization was observed after annealing the schemes at 400.degree. C. for 100 hours and at 900.degree. C. for 30 minutes. Thermal cycling experiments in air from -65 to 155.degree. C. and adhesion tests were performed. Various embodiments are disclosed.
    Type: Grant
    Filed: August 18, 1995
    Date of Patent: September 5, 2000
    Assignee: California Institute of Technology
    Inventors: Andreas Bachli, Elzbieta Kolawa, Marc-Aurele Nicolet, Jan W. Vandersande
  • Patent number: 5729054
    Abstract: A preferred embodiment of this invention comprises an oxidizable layer (e.g. TiN 50), an noble-metal-insulator-alloy barrier layer (e.g. Pd-Si-N 34) overlying the oxidizable layer, an oxygen stable layer (e.g. platinum 36) overlying the noble-metal-insulator-alloy layer, and a high-dielectric-constant material layer (e.g. barium strontium titanate 38) overlying the oxygen stable layer. The noble-metal-insulator-alloy barrier layer substantially inhibits diffusion of oxygen to the oxidizable layer, thus minimizing deleterious oxidation of the oxidizable layer.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: March 17, 1998
    Assignee: Texas Instruments Incorporated
    Inventors: Scott R. Summerfelt, Jason Reid, Marc Nicolet, Elzbieta Kolawa
  • Patent number: 5696018
    Abstract: A preferred embodiment of this invention comprises an oxidizable layer (e.g. TiN 50), an noble-metal-insulator-alloy barrier layer (e.g. Pd-Si-N 34) overlying the oxidizable layer, an oxygen stable layer (e.g. platinum 36) overlying the noble-metal-insulator-alloy layer, and a high-dielectric-constant material layer (e.g. barium strontium titanate 38) overlying the oxygen stable layer. The noble-metal-insulator-alloy barrier layer substantially inhibits diffusion of oxygen to the oxidizable layer, thus minimizing deleterious oxidation of the oxidizable layer.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: December 9, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: Scott R. Summerfelt, Jason Reid, Marc Nicolet, Elzbieta Kolawa
  • Patent number: 5622893
    Abstract: A preferred embodiment of this invention comprises an oxidizable layer (e.g. TiN 50), an noble-metal-insulator-alloy barrier layer (e.g. Pd-Si-N 34) overlying the oxidizable layer, an oxygen stable layer (e.g. platinum 36) overlying the noble-metal-insulator-alloy layer, and a high-dielectric-constant material layer (e.g. barium strontium titanate 38) overlying the oxygen stable layer. The noble-metal-insulator-alloy barrier layer substantially inhibits diffusion of oxygen to the oxidizable layer, thus minimizing deleterious oxidation of the oxidizable layer.
    Type: Grant
    Filed: August 1, 1994
    Date of Patent: April 22, 1997
    Assignees: Texas Instruments Incorporated, California Institute of Technology
    Inventors: Scott R. Summerfelt, Jason Reid, Marc Nicolet, Elzbieta Kolawa