Abstract: A DPI circuit reduces noise effects in an ESD circuit when coupled between an ESD circuit and a protected pin. The DPI circuit includes an NMOS transistor coupled between an output node and a lower rail and a charge pump coupled between the input node and the gate of the first NMOS transistor. A resistor is coupled between the gate of the first NMOS transistor and the lower rail.

Abstract: A DPI circuit reduces noise effects in an ESD circuit when coupled between an ESD circuit and a protected pin. The DPI circuit includes an NMOS transistor coupled between an output node and a lower rail and a charge pump coupled between the input node and the gate of the first NMOS transistor. A resistor is coupled between the gate of the first NMOS transistor and the lower rail.

Abstract: A roll-out wheel has a base housing secured to a working surface. A rolling arm having a lever end and a working end pivots about a hinge point in the housing. A hand wheel and a pipe chuck are rotatably attached to the working end by a rolling sleeve. A pipe to be welded is securable on the pipe chuck and rotatable in unison with the hand wheel. Rotation of the hand wheel permits welding about the perimeter of the pipe without moving the welding tool. A clamping mechanism can permit or prevent rotation of the hand wheel. A pivoting mechanism can raise or lower the working end.

Abstract: A roll-out wheel has a base housing secured to a working surface. A rolling arm having a lever end and a working end pivots about a hinge point in the housing. A hand wheel and a pipe chuck are rotatably attached to the working end by a rolling sleeve. A pipe to be welded is securable on the pipe chuck and rotatable in unison with the hand wheel. Rotation of the hand wheel permits welding about the perimeter of the pipe without moving the welding tool. A clamping mechanism can permit or prevent rotation of the hand wheel. A pivoting mechanism can raise or lower the working end.

Abstract: A transmission gate self-biases its transistors to provide a constant gate biasing that provides a consistent path for an input signal to be cleanly passed to the gate's output and protects the transistors' gate oxide in cases of high input signals. An array of matched transistors are arranged to be biased by a voltage input node and with a current source configured to provide a bias current across individual transistors of the array of matched transistors. A current sink is configured to sink the bias current across the individual transistors to set a bias voltage at a voltage input node to a multiple of a gate-to-source voltage for the individual transistors of the array of matched transistors. A different set of transistors is configured to provide a signal path for an analog input signal.

Abstract: A transmission gate self-biases its transistors to provide a constant gate biasing that provides a consistent path for an input signal to be cleanly passed to the gate's output and protects the transistors' gate oxide in cases of high input signals. An array of matched transistors are arranged to be biased by a voltage input node and with a current source configured to provide a bias current across individual transistors of the array of matched transistors. A current sink is configured to sink the bias current across the individual transistors to set a bias voltage at a voltage input node to a multiple of a gate-to-source voltage for the individual transistors of the array of matched transistors. A different set of transistors is configured to provide a signal path for an analog input signal.