Abstract: A process for a memory transistor (e.g. flash-EEPROM cell), which includes forming an isolation-spacer between a control gate and an erase line over a floating gate by first growing a thin thermal oxide to be in contact with the first sidewall of control gate and thereafter depositing fluorinated-TEOS or tetramethylsilane (TMS) based LPCVD oxide at low temperature of about 250 degrees centigrade. The choice of deposited oxide have lower dielectric constant than that of thermal silicon dioxide which lowers the parasitic capacitance between word lines and erase lines and thereby increases speed performance. The process can be used to form low-K (low dielectric constant) dielectric insulation between word lines of in all types of memory chips including DRAM and Flash NVM.

Abstract: A process for a memory transistor (e.g. flash-EEPROM cell), which includes forming an isolation-spacer between a control gate and an erase line of over a floating gate by first growing a thin thermal oxide to be in contact with the first sidewall of control gate and thereafter depositing fluorinated-TEOS or tetramethylsilane (TMS) based LPCVD oxide a low temperature of about 250 degrees centigrade. The choice of deposited have lower dielectric constant than that of thermal silicon dioxide which lowers the parasitic capacitance between word lines and erase lines and thereby increases speed performances. The process prevents the formation of a poly-oxide beak under the control gate, thereby the first insulator between the control gate and the floating gate has a uniform thickness. The transistor programs efficiently, is reliable, has low manufacture cost and is physically and electrically down scalable.

Abstract: A process for a split-gate transistor (e.g. flash-EEPROM cell), which includes a channel's drain-area, a first insulator disposed over the drain-area and a first gate disposed over the first insulator, and a control (select) gate is insulatively disposed over the channel's source-area and over a channel's gap-area located between the drain area and source area.It includes growing a second thin thermal oxide to be in contact with the first gate and the channel's source-area and gap-area that is adjacent he channel's drain-area, depositing TEOS based LPCVD oxide on the second oxide and then depositing the control gate on the first gate and over the channel's source and gap areas.It prevents the formation of an oxide beak under the first gate, thereby the first insulator has a uniform thickness. The polysilicon of the control gate conforms to the side wall of the first gate and does not protrude under the first gate.

Abstract: The invention enables random read and write operations into cells in an array of a memory device. It includes a decoding scheme wherein the memory chip has a row address bit which is used for the row decoding also participates (in some embodiments) in the column and bit-line decoding process.The data is routed to and from the alongated bit-line by a selector at one bit-line end and/or by a separate selector at the other end of the same bit-line. This is accomplished by address circuitry and column selection circuitry. Data is read out and processed by a signal processing means such as a sense amplifier and/or data buffer.In some embodiments such as flash EEPROM device, programming voltage VPP is applied to the bit-line only through the selector at one end of the bit-line.

Abstract: The invention enables random read and write operations into cells in an array that contains connections from the memory cells that include at least one field effect transistor (FET transistor) to embedded bit line segments which are selectively isolatable and selectively expandable to achieve compactness of number of cell per unit area.In a given segment of the array a first select transistor is connected between a given embedded bit line segment and a first access bit line which functions as a path from a first reference voltage to the drain of a first FET memory transistor set when the first select transistor is turned off, and wherein the first access bit line functions as a path from the source of a second FET memory transistor set to a second reference voltage when the first select transistor is turned on.

Abstract: A current mirror circuit for fast programming of semiconductor memory cells and for ease of testing and verifying the condition of the memory chips. The current mirror includes a reference branch and multiple output branches. At least one output branch connects to a programmable memory cell through FET transistors and the programming current flows from the output branch to the memory cell to supply it with the programming current. When the programming of the memory cells is accomplished the drain current of the memory cell is reduced to be below that of the current of the reference branch of the current mirror. Because the memory cell is connected in series with the output branch of the current mirror, the current of the output branch is also reduced to be below the current of the reference branch.

Abstract: The invention enables random read and write operations into cells in an array that contains staggered source or drain connections from the memory cells in a given column. The invention comprises only one row decoder providing the required voltages to the read word lines during reading, programming and erase operations. The invention reduces the effective programming time of a single cell and of an entire row of cells that program using hot electrons.According to another aspect of the invention the asymmetry in programming of split gate EEPROM is used to reverse bias the cell so a plurality of digital bits that were stored by D/A converter in the cell according to a curve are read out by an A/D converter with large voltage difference between logical states.

Abstract: The invention enables random read and write operations into cells in an array that contains staggered source or drain connections from the memory cells in a given column. The invention comprises only one row decoder providing the required voltages to the read word lines during reading, programming and erase operations. The invention reduces the effective programming time of a single cell and of an entire row of cells that program using hot electrons.According to another aspect of the invention the asymmetry in programming of split gate EEPROM is used to reverse bias the cell so a plurality of digital bits that were stored by D/A converter in the cell according to a curve are read out by an A/D converter with large voltage difference between logical states.

Abstract: An EEPROM memory cell structure and architecture that achieve very high speed programming with low power. The cell has four control terminals. The structure utilizes programming and erasure by electron tunneling only. The structure allows programming by hot electrons from the substrate and erasure by electron tunneling between polysilicon layers. A process for forming the structure results in final feature size for the floating gate and the space between floating gates in a memory array to be significantly smaller than achievable by photolithography equipment's resolution capability.

Abstract: An EEPROM memory cell structure and architecture that achieve very high speed programming with low power. The cell has four control terminals. The structure utilizes programming and erasure by electron tunneling only. The structure allows programming by hot electrons from the substrate and erasure by electron tunneling between polysilicon layers. A process for forming the structure results in final feature size for the floating gate and the space between floating gates in a memory array to be significantly smaller than achievable by photolithography equipment's resolution capability.

Abstract: AN EEPROM memory cell structure and architecture that achieve very high speed programming with low power. The cell has four control terminals. The structure utilizes programming and erasure by electron tunneling only. The structure allows programming by hot electrons from the substrate and erasure by electron tunneling between polysilicon layers. A process for forming the structure results in final feature size for the floating gate and the space between floating gates in a memory array to be significantly smaller than achievable by photolithography equipment's resolution capability.

Abstract: The invention enables random read and write operations into cells in an array that contains staggered source or drain connections from the memory cells in a given column. It includes a decoding scheme wherein the memory chip has a row address bit which is used for the row decoding also participating in the bit line decoding process. The invention comprises only one row decoder providing the required voltages to the read word lines during reading, programming and page and flash erase operations. The invention expands the feature of the reduction in programming time of non-volatile memories from a single cell to the entire row of cells that program using hot electrons. The invention reduces the diffusion isolation spacing between bit-lines by using shield transistors. A current mirror with multiple branches is used as part of a power switch to control the supply of 5 or 12 volts to various circuit block of the EEPROM chip.

Abstract: An improved EEPROM having a cell including source and drain diffusions, a channel having a source region and a drain region, a floating gate that is disposed only over the drain region of the channel and has a coupling edge disposed adjacent to the drain diffusion to strongly capacitively couple the floating gate to the drain. During programming the floating gate voltage is increased, due to the capacitive coupling of the floating gate to the drain, which in turn inverts the drain region of the channel. The inversion of the drain region increases the coupling of the floating gate to the drain to increase electron tunneling to program the floating gate. Only three control signals are required to read, program, and erase the cell.

Abstract: An electrically readable and writable memory cell structure and array architecture formed on a semiconductor substrate to achieve very high speed programming with low power. The cell includes a superior storage capacitor structure including a textured surface of at least one of the plates and a dielectric sandwich between the plates that prevents charge loss in all modes of the electrical operation of the memory cell while increasing the capacitance of the capacitor which also reduces the programming (writing a first logical state) voltage of the memory cell. The structure utilizes programming and erasure by electron tunneling only. The structure allows programming by hot electrons from the substrate and erasure by electron tunneling between polysilicon layers. A process for forming the structure results in final feature size for the floating gate and the space between floating gates in a memory array to be significantly smaller than achievable by photolithography equipment's resolution capability.

Abstract: A process for the fabrication of an EEPROM structure requiring only two poly layers that utilize hot electrons from the substrate for programming and poly-to-poly electron tunneling for erasure. The structure is advantageously utilized in an Ultra Violate Light Erasable PROM.The process results in a structure that allows programming and erasure by electron tunneling only.

Abstract: An EEPROM memory cell structure and architecture that achieve very high speed programming with low power. The cell has four control terminals. The structure utilizes programming and erasure by electron tunneling only. The structure allows programming by hot electrons from the substrate and erasure by electron tunneling between polysilicon layers. A process for forming the structure results in final feature size for the floating gate and the space between floating gates in a memory array to be significantly smaller than achievable by photolithography equipment's resolution capability.

Abstract: An EEPROM memory cell structure and architecture that achieve very high speed programming with low power. The cell has four control terminals. The structure utilizes programming and erasure by electron tunneling only. The structure allows programming by hot electrons from the substrate and erasure by electron tunneling between polycrystalline silicon layers. A process for forming the structure results in final feature size for the floating gate and the space between floating gates in a memory array to be significantly smaller than achievable by photolithography equipment's resolution capability.

Abstract: An improved EEPROM having a cell including source and drain diffusions, a channel having a source region and a drain region, a floating gate that is disposed only over the drain region of the channel and has a coupling edge disposed adjacent to the drain diffusion to strongly capacitively couple the floating gate to the drain. During programming the floating gate voltage is increased, due to the capacitive coupling of the floating gate to the drain, which in turn inverts the drain region of the channel. The inversion of the drain region increases the coupling of the floating gate to the drain to increase electron tunneling to program the floating gate. Only three control signals are required to read, program, and erase the cell.

Abstract: An EEPROM structure requiring only two poly layers that utilizes hot electrons from the substrate for programming and poly-to-poly electron tunnelling for erasure. The structure is also advantageously utilized in an Ultra Violet Light Erasable PROM. The structure allows programming and erasure by electron tunnelling only.

Abstract: An improved E.sup.2 PROM cell including an isolated control diffusion region strongly capacitively coupled to the floating gate. This control region is coupled to the drain during programming and efficiently couples the programming voltage to the floating gate to induce tunnelling. Only three control signals are required to read, program, or erase the cell.