Abstract: The invention provides a system and method for reducing pin count in an integrated circuit (IC) when interfacing to a synchronous dynamic random access memory (SDRAM). The SDRAM has a plurality of address lines and a plurality of data lines. The method includes connecting together the plurality of data lines and the plurality of address lines. The IC interfaces to the SDRAM through the connected plurality of address lines and the plurality of data lines.

Abstract: The invention provides a system and method for reducing pin count in an integrated circuit (IC) when interfacing to a synchronous dynamic random access memory (SDRAM). The SDRAM has a plurality of address lines and a plurality of data lines. The method includes connecting together the plurality of data lines and the plurality of address lines. The IC interfaces to the SDRAM through the connected plurality of address lines and the plurality of data lines.

Abstract: A transport stream decoder/demultiplexer is provided which includes a program clock recovery circuit for recovering a program clock from program clock reference (PCR) values contained in selected transport packets. A processor is provided for extracting elementary stream data from transport packets labeled with packet identification codes (PIDs) that are specified by a host processor. The processor separately stores the elementary stream data of each stream. A host processor interface is also provided for transferring data between an external host processor and the program clock recovery circuit. A memory manager may be provided for storing the data extracted by the processor for each elementary stream in a corresponding queue. The queues may be maintained by the memory manager in an external RAM. A descrambler interface may be provided for transferring scrambled data and data derived from conditional access information between the processor and an external descrambler.