Abstract: An in-memory computation device for performing an in-memory computation operation has a programming circuit. The programming circuit maps a signed computational weight into a group of memory cells of the IMC device. The group of cells has a first set of cells and a second set of cells that are configured to provide, during the execution of the in-memory computation operation, current contributions as a function of their respective programming and having opposite signs to each other. The programming circuit programs a memory cell based on the computational weight, detects a programming error of the memory cell of the first set of cells, and programs a memory cell of the second set of cells to account for the detected programming error.

Abstract: A group of memory cells includes a first cell with a first number of bits, coupled to a first bit line and programmable with a first weight and a second cell with a second number of bits, coupled to a second bit line and programmable with the first weight. An activation circuit applies first and second activation signals to the first and second cells during first and second windows, respectively. The activation signals have respective durations as a function of an input value and, optionally, a number of bits of the first or second cell. A read circuit generates first and second signals indicative of a time integral of current in the first and second bit lines during the first and second windows, respectively, and outputs a digital signal indicative of a sum between the first and second signals, optionally also as a function of number of bits.

Abstract: A memory device includes programmable memory cells and a programming circuit for programming a selected memory cell to a target logic state by applying one or more programming current pulses. A temperature sensor operates to sense a temperature of the memory device. A reading circuit reads a current logic state of the selected memory cell after a predetermined programming current pulse of the programming current pulses. The reading circuit includes a sensing circuit that senses a current logic state of the selected memory cell according to a comparison between a reading electric current depending on the current logic state of the selected memory cell and a reference current. An adjusting circuit adjusts one or the other of the reading electric current and the reference electric current to be provided to the sensing circuit according to the temperature of the memory device.

Abstract: A memory device includes programmable memory cells and a programming circuit for programming a selected memory cell to a target logic state by applying one or more programming current pulses. A temperature sensor operates to sense a temperature of the memory device. A reading circuit reads a current logic state of the selected memory cell after a predetermined programming current pulse of the programming current pulses. The reading circuit includes a sensing circuit that senses a current logic state of the selected memory cell according to a comparison between a reading electric current depending on the current logic state of the selected memory cell and a reference current. An adjusting circuit adjusts one or the other of the reading electric current and the reference electric current to be provided to the sensing circuit according to the temperature of the memory device.

Abstract: A method for programming a phase-change-memory device of a differential type comprises, in a first programming mode, supplying, during a first time interval, a same first programming current, of a type chosen between a SET current and a RESET current, to all the direct and complementary memory cells that are to be programmed with said first programming current; and, in a second programming mode, supplying, during a second time interval, a same second programming current, of the other type chosen between a SET current and a RESET current, to all the direct and complementary memory cells that are to be programmed with said second programming current, thus completing, in just two time steps, writing of a logic word in the memory device.

Abstract: A method for programming a phase-change-memory device of a differential type comprises, in a first programming mode, supplying, during a first time interval, a same first programming current, of a type chosen between a SET current and a RESET current, to all the direct and complementary memory cells that are to be programmed with said first programming current; and, in a second programming mode, supplying, during a second time interval, a same second programming current, of the other type chosen between a SET current and a RESET current, to all the direct and complementary memory cells that are to be programmed with said second programming current, thus completing, in just two time steps, writing of a logic word in the memory device.

Abstract: In accordance with an embodiment, a memory includes: a memory element, a sense amplifier circuit configured to sense a difference during a sense operation between a sense current passing through the memory element and a reference current, and a margin current branch coupled in parallel with the memory element and configured to selectively add a margin current to the sense current.

Abstract: An embodiment method includes storing, in each of a first plurality of memory locations of a memory, an address of another of the first plurality of memory locations, and reading, from a bus signal received at the memory, an address of a first one of the first plurality of memory locations. The method further includes reading data stored in the first one of the first plurality of memory locations, and determining, using the read data, whether a read error has occurred.

Abstract: In accordance with an embodiment, a circuit includes a sense amplifier circuit configured to sense a difference between a first current based on a direct memory bit and a second current based on a complementary memory bit. The direct memory bit is coupled to a first input of the sense amplifier circuit, and the complementary memory bit is coupled to a second input of the sense amplifier circuit. A controller is configured to, during a sense operation, selectively add a first margin current to the first current, and during the sense operation, selectively add a second margin current to the second current.

Abstract: An embodiment method includes storing, in each of a first plurality of memory locations of a memory, an address of another of the first plurality of memory locations, and reading, from a bus signal received at the memory, an address of a first one of the first plurality of memory locations. The method further includes reading data stored in the first one of the first plurality of memory locations, and determining, using the read data, whether a read error has occurred.

Abstract: In accordance with an embodiment, a memory includes: a memory element, a sense amplifier circuit configured to sense a difference during a sense operation between a sense current passing through the memory element and a reference current, and a margin current branch coupled in parallel with the memory element and configured to selectively add a margin current to the sense current.

Abstract: In accordance with an embodiment, a circuit includes a sense amplifier circuit configured to sense a difference between a first current based on a direct memory bit and a second current based on a complementary memory bit. The direct memory bit is coupled to a first input of the sense amplifier circuit, and the complementary memory bit is coupled to a second input of the sense amplifier circuit. A controller is configured to, during a sense operation, selectively add a first margin current to the first current, and during the sense operation, selectively add a second margin current to the second current.

Abstract: A differential PCM memory may include first and second PCM elements, and a sense amplifier circuit configured to sense a difference between first and second sense currents passing through the first and second PCM elements, respectively, during a sense operation. The differential PCM memory may include a first margin current branch coupled in parallel with the first PCM element and configured to selectively add a first margin current to the first sense current, and a second margin current branch coupled in parallel with the second PCM element and configured to selectively add a second margin current to the second sense current.