Abstract: A charge pump (2) is supplied to reset in rated conditions the error signal of a phase-locked loop of the type whereby a phase detector (1) periodically supplies this pump (2) with a first and second impulse having emission instants dependent on the phase ratio between phase-locked loop input signals and are allocated to control circuit output increase or decrease respectively by means of ring filter (3a, 3b). The pump features loops (21, 22, 23, 24, 28) to transform the first and second impulse into a first and second voltage signal of longer duration than maximum impulse duration and featuring values the difference of which depends on the phase ratio between the loop input signals and to generate a signal in a current representative of such difference.

Abstract: A phase locked loop circuit includes an input comparator (2) capable of generating a deviation signal which can be used for driving an oscillator (5) so as to generate an output signal (CLKOUT) locked to the input signal. The oscillator (5) can operate according to a plurality of characteristics under the control of a control circuit (8) including searching circuits arranged to carry out a first search phase by scanning the family of characteristics admitted for the operation of the oscillator (5) by bands of progressively reduced width, according to a general, dichotomic procedure. Upon completion of this first search phase, additional circuits of fine search are destined to identify the optimum operating point, compensating possible fluctuations of the characteristics.

Abstract: The delay element consists of a differential amplifier (M15, M8, M2, M6, M5) in which the load transistors (M2, M5) are associated to respective gate biasing transistors (M21, M22) connected in a source follower configuration, and to feedback transistors (M3, M4), which implement a negative impedance in parallel to a positive impedance represented by each of the load transistors (M2, M5). The modulation of the delay is achieved by modulating the bias currents of the load transistors (M2, M5), the feedback transistors (M3. M4) and the gate biasing transistors (M21, M22).

Abstract: A device (DC) is provided for compensating process and operating parameters variations in a CMOS integrated circuit. The device comprises means (CP, CT) for generating a first and a second compensation signals which depend on quality indexes of the fabrication process of the P and N transistors of the integrated circuit and on the operating temperature, and which are capable of compensating deviations of the controlled quantity from the desired value, due to the deviation of the quality indexes and temperature, respectively, from a typical value which would originate the desired value for the output parameter. The compensating device also can be implemented in the form of CMOS integrated circuit, preferably jointly with the device (OS) to be subjected to compensation (FIG. 1).

Abstract: A current reference generator comprises a pair of identical units (G1, G2) which generate respective current references (I1, I2), and a circuit (CL) for the linear combination of the two references. In each of the two units, the elements (S1, S2) which, by their current-voltage characteristics, determine the working point comprise respectively a single transistor (T1) and a pair of transistors (T2, T3), of the same type as the first, connected in series. A differential amplifier (AD) maintains stable the working point of the respective unit as power supply voltage varies. (FIG.