Abstract: A media management operation is initiated on a plurality of management units of one or more memory devices managed by the controller. A first error status and second error status associated with a read stage of the media management operation performed on a first management unit of the plurality of management units is received. An error correction operation on the first management unit is performed responsive to determining that the first error status and the second error status indicate a correctable error in the first management unit. An entry mapping a logical address to a physical address associated with the first management unit is locked responsive to determining that no spare management unit is available.

Abstract: An apparatus can include a plurality of memory devices and a memory controller coupled to the plurality of memory devices via a plurality of memory channels. The plurality of memory channels are organized as a plurality of channel groups. The memory controller comprises a plurality of memory access request/response buffer sets, and each memory access request/response buffer set of the plurality of memory access request/response buffer sets corresponds to a different one of the plurality of channel groups.

Abstract: A channel width can depend on a quantity of memory units (e.g., memory dice) that forms a channel as well as a size of the memory units. A memory system can operate with memory units configured to exchange (e.g., transfer to and/or from) data at a rate of smaller granularity that can provide more various options for channel widths, which can further allow a fine-tuned optimization of the memory system in association with its bandwidth and latency in transferring data from and/or to the memory units. The channels whose channel width is fine-tuned with such memory units can be further used to provide a reliability, availability, and serviceability (RAS) protection, such as a redundant array of independent disks (RAID) protection.

Abstract: Methods, systems, and devices for managed memory systems with multiple priority queues are described. Memory access commands may be received from a host and stored in a command queue. First and second subsets of the commands, respectively associated with first and second priorities, may be determined. The first and second subsets may be routed from the command queue to first and second queues, respectively. The first and second subsets may be processed from the first and second queues to third and fourth queues, respectively, at a storage controller, according to first and second processes that may be run concurrently according to parameters for prioritization between the first and second priorities. Data associated with the commands may be received from the host, temporarily stored in a buffer, then moved to a storage memory (for write commands) or retrieved from the storage memory, temporarily stored in the buffer, then transmitted to the host (for read commands).

Abstract: A system includes a memory device; and a processing device coupled to the memory device, the processing device to perform operations including: identifying at least one unusable management unit (UMU) in a plurality of management units that are designated for wear leveling; storing, in a data structure, a physical address and a logical address of the identified at least one UMU; excluding, from a physical address space for wear leveling, the physical address of the identified at least one UMU; and performing a wear leveling operation using the physical address space, wherein the wear leveling operation moves data of a management unit to a neighboring management unit in a circular manner.

Abstract: Systems, apparatuses, and methods related to a memory controller for cache bypass are described. An example memory controller can be coupled to a memory device. The example memory controller can include a cache including a cache sequence controller configured to determine a quantity of a given type of result of cache look-up operations, determine the quantity satisfies a bypass threshold, and cause performance of a bypass memory operation that bypasses the cache and accesses the memory device.

Abstract: A variety of applications can include a memory device having chained mapping with compression of received data. The memory device can include a mapping table having an entry location to associate a virtual page with a physical address of a first stripe of compressed data of the virtual page. A controller of the memory device, responsive to the data of the virtual page being compressed data, can load information about a second stripe of the compressed data into extra locations in the first stripe different from locations for compressed data of the virtual page in the first stripe. Additional apparatus, systems, and methods are disclosed.

Abstract: A variety of applications can include a memory device having dynamic page mapping with compression. The memory device can include a mapping table having an entry location to associate a virtual page with a physical address of a first stripe of data of the virtual page. The entry location can include a flag along with the physical address of the first stripe. The flag can identify data of the virtual page as being compressed or uncompressed. A controller of the memory device, responsive to the flag identifying the data of virtual page being compressed, is structured to generate a format of compressed data of the first stripe with a header. The header can include a count of additional physical addresses to store compressed data of the virtual page and the additional physical addresses. Additional apparatus, systems, and methods are disclosed.

Abstract: Provided in a central controller system, is a system and method to identify and mitigate errors on a die containing mission critical logical-to-physical addressing information. The logical-to-physical (L2P) addressing information is essential for translating logical memory addresses for uncompressed data to physical addresses for compressed data. When a die containing L2P data is detected as being corrupted, the corrupted data is corrected, and all the data is moved to an uncorrupted die at a specified offset from the original address of the die.

Abstract: A variety of applications can include a memory device implementing a dual compression scheme. A memory subsystem of the memory device can be arranged into multiple regions. A first region of the memory subsystem can be used to store non-compressible data. A second region can be used to store compressible data. The second region can have a first subregion and a second subregion. The first subregion can be used to accept compressible data as non-compressed data corresponding to a compression ratio being less than a threshold compression ratio. The second subregion can be used to accept compressed data corresponding to a compression ratio being greater than the threshold compression ratio. Additional apparatus, systems, and methods are disclosed.

Abstract: Provided is a device that includes an interface operatively coupled to a locked redundant array of independent disks (LRAID) including M (M>1) memory dice, the M memory dice stores stripes of data, and each stripe spanning over the M memory dice; and control circuitry that performs data compression on data to generate compressed data; stores the compressed data in the stripes; generates parity data of each stripe; determines, for each stripe, memory dice required to store the compressed data; determines, for each stripe, whether memory dice required to store the compressed data in each stripe is N memory dice or less; where N is an integer less than M; and determines, for each stripe, which stripes will store the parity data of a respective stripe based on the determination of whether the memory dice required to store the compressed data in the respective stripe is N memory dice or less.

Abstract: An apparatus can include a plurality of memory devices and a memory controller coupled to the plurality of memory devices via a plurality of memory channels. The plurality of memory channels can be each organized as a plurality of channel groups that can be operated as independent RAS channels (e.g., channels for independent RAS accesses). Data received at the memory controller via different memory channels of one RAS channel can be aligned at various circuits and/or components of the memory controller.

Abstract: A channel width can depend on a quantity of memory units (e.g., memory dice) that forms a channel as well as a size of the memory units. A memory system can operate with memory units configured to exchange (e.g., transfer to and/or from) data at a rate of smaller granularity that can provide more various options for channel widths, which can further allow a fine-tuned optimization of the memory system in association with its bandwidth and latency in transferring data from and/or to the memory units. The channels whose channel width is fine-tuned with such memory units can be further used to provide a reliability, availability, and serviceability (RAS) protection, such as a redundant array of independent disks (RAID) protection.

Abstract: Provided is a device that includes an interface operatively coupled to a locked redundant array of independent disks including M (M>1) memory dice, the M memory dice stores stripes of data, and each stripe spanning over the M memory dice; and control circuitry that performs data compression on data to generate compressed data; stores the compressed data in the stripes; generates parity data of each stripe; determines, for each stripe, memory dice required to store the compressed data; determines, for each stripe, whether the memory dice required to store the compressed data in each stripe is N memory dice or less; where N is an integer less than M; and determines, for each stripe, which stripes will store the parity data of a respective stripe based on the determination of whether the memory dice required to store the compressed data in the respective stripe is N memory dice or less.

Abstract: Systems, apparatuses, and methods related to a controller for managing metrics and telemetry are described. A controller includes a front end portion, a central controller portion, a back end portion, and a management unit. The central controller portion can include a cache to store data associated with the performance of the memory operations, metric logic configured to collect metrics related to performance of the memory operations, load telemetry logic configured to collect load telemetry associated with performance of the memory operations within a threshold time, and a storage area to store the collected metrics and the collected load telemetry. The management unit memory of the controller can store metrics and load telemetry associated with monitoring the characteristics of the memory controller, and based on the stored metrics and load telemetry, alter at least one characteristic of the computing system.

Abstract: A memory controller can include a front end portion configured to interface with a host, a central controller portion configured to manage data, a back end portion configured to interface with memory devices. The memory controller can include interface management circuitry coupled to a cache and a memory device. The memory controller can receive, by the interface management controller, a first signal indicative of data associated with a memory access request from a host. The memory controller can transmit a second signal indicative of the data to cache the data in a first location in the cache. The memory controller can transmit a third signal indicative of the data to cache the data in a second location in the cache.

Abstract: Described apparatuses and methods relate to a read data path for a memory system. The memory system may include logic that receives data and associated metadata from a memory. The logic may perform a reliability check on the data using the associated metadata to determine if the data has an error. If the data is determined not to include an error, the data may be transmitted to a requestor. If the data is determined to include an error, however, a data recovery process may be initiated to recover the data. This may reduce a likelihood the memory system returns corrupted data to a requestor. The memory system may process a different read request at least partially in parallel with the data recovery process to increase throughput or reduce latency. In some cases, the data recovery process may involve one or more techniques related to redundant array of disks (RAID) technology.

Abstract: An apparatus can include a plurality of memory devices and a memory controller coupled to the plurality of memory devices via a plurality of memory channels. The plurality of memory channels can be each organized as a plurality of channel groups that can be operated as independent RAS channels (e.g., channels for independent RAS accesses). Data received at the memory controller via different memory channels of one RAS channel can be aligned at various circuits and/or components of the memory controller.

Abstract: Systems, apparatuses, and methods related to a controller for managing metrics and telemetry are described. A controller includes a front end portion, a central controller portion, a back end portion, and a management unit. The central controller portion can include a cache to store data associated with the performance of the memory operations, metric logic configured to collect metrics related to performance of the memory operations, load telemetry logic configured to collect load telemetry associated with performance of the memory operations within a threshold time, and a storage area to store the collected metrics and the collected load telemetry. The management unit memory of the controller can store metrics and load telemetry associatAND ed with monitoring the characteristics of the memory controller, and based on the stored metrics and load telemetry, alter at least one characteristic of the computing system.

Abstract: Systems, apparatuses, and methods related to a controller for managing multiple types of memory are described. A controller includes a front end portion, a central controller portion, a back end portion, and a management unit can manage a first type of memory device that operates according to a first set of timing characteristics and a second type of memory device that operates according to a second set of timing characteristics. The central controller portion is configured to cause performance of a memory operation and comprises a cache memory to buffer data associated performance of the memory operation, a security component configured to encrypt the data before storing the data in the first type of memory device or the second type of memory device, and error correction code (ECC) circuitry to ECC encode and ECC decode the data.