Abstract: The present disclosure relates to a direct memory access circuit comprising at least one data path (Ch1, Ch2, Ch3, Chs) coupling an input port of a master interface to an output port of the master interface. The at least one data path comprises a first data path (Ch1). The first data path (Ch1) has a pipelined structure. The first data path (Ch1) comprises a first circuit (200, 200B) configured to apply one among a Boolean to arithmetic masking conversion and an arithmetic to Boolean masking conversion to data propagated by the first data path (Ch1).

Abstract: A digital circuit for including a scalar product between two vectors (a0, a1, . . . , ai, . . . , aN-1) and (s0, s1, . . . , si, . . . , sN-1). The digital circuit includes a multiplier, an accumulator including at least one adder and a register, as well as a control circuit of the accumulator. At a clock tick of index i, the multiplier is configured to compute the result ri of the multiplication ai×si, and the accumulator is configured to add ri with the current value of the register. Afterwards, the result of the addition is memorised in the register. The control circuit is configured to control the accumulator so as to perform the addition in an approximate manner for at least one addition amongst the N additions of the computation of the scalar product. In particular, the digital circuit is intended to be used in an electronic device implementing a cryptographic algorithm based on a “Learning With Errors” (LWE) technology.