Abstract: The disclosure relates to integrated circuits and methods including one or more rows of transistors. In an embodiment, an integrated circuit includes a row of bipolar transistors including a plurality of first conduction regions, a second conduction region, and a common base between the first conduction regions and the second conduction region. An insulating trench is in contact with each bipolar transistor of the row of bipolar transistors. A conductive layer is on the insulating trench and the common base between the first conduction regions. A spacer layer is between the conductive layer and the first conduction regions.

Abstract: The disclosure relates to integrated circuits and methods including one or more rows of transistors. In an embodiment, an integrated circuit includes a row of bipolar transistors including a plurality of first conduction regions, a second conduction region, and a common base between the first conduction regions and the second conduction region. An insulating trench is in contact with each bipolar transistor of the row of bipolar transistors. A conductive layer is on the insulating trench and the common base between the first conduction regions. A spacer layer is between the conductive layer and the first conduction regions.

Abstract: The disclosure relates to integrated circuits and methods including one or more rows of transistors. In an embodiment, an integrated circuit includes a row of bipolar transistors including a plurality of first conduction regions, a second conduction region, and a common base between the first conduction regions and the second conduction region. An insulating trench is in contact with each bipolar transistor of the row of bipolar transistors. A conductive layer is on the insulating trench and the common base between the first conduction regions. A spacer layer is between the conductive layer and the first conduction regions.

Abstract: The disclosure relates to integrated circuits and methods including one or more rows of transistors. In an embodiment, an integrated circuit includes a row of bipolar transistors including a plurality of first conduction regions, a second conduction region, and a common base between the first conduction regions and the second conduction region. An insulating trench is in contact with each bipolar transistor of the row of bipolar transistors. A conductive layer is on the insulating trench and the common base between the first conduction regions. A spacer layer is between the conductive layer and the first conduction regions.

Abstract: The invention relates to a method for preparing a thin film of at least one compound of formula AM4X8, where: A is Ga or Ge; M is V, Nb, Ta or Mo; and X is S or Se. Said method includes the following steps: i) a step of forming a thin film of at least one compound of formula AM4X8 by the magnetron spraying of a target including at least one compound of said formula AM4X8, in an atmosphere including at least one inert gas; and ii) a step of annealing the thin film formed during step i) by heat treating; wherein step i) and/or step ii) are carried out in the presence of sulphur when X is S or in the presence of selenium when X is Se.

Abstract: The invention relates to a method for preparing a thin film of at least one compound of formula AM4X8, where: A is Ga or Ge; M is V, Nb, Ta or Mo; and X is S or Se. Said method includes the following steps: i) a step of forming a thin film of at least one compound of formula AM4X8 by the magnetron spraying of a target including at least one compound of said formula AM4X8, in an atmosphere including at least one inert gas; and ii) a step of annealing the thin film formed during step i) by heat treating; wherein step i) and/or step ii) are carried out in the presence of sulphur when X is S or in the presence of selenium when X is Se.