Patents by Inventor Emerson Mamaril Enipin

Emerson Mamaril Enipin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • MCM package isolation through leadframe design and package saw process
    Patent number: 11862479
    Abstract: A method of making a semiconductor device includes mounting at least two semiconductor dies to a die pad of a leadframe in spaced apart relation to each other, the leadframe having a plurality of preformed leads, electrically connecting each semiconductor die to at least one preformed lead of the leadframe, forming a molding structure including at least part of the semiconductor dies and the preformed leads of the leadframe, and forming a trench in the molding structure in a space between the at least two semiconductor dies, the trench separating the die pad into first and second die pad portions.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: January 2, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Bernard Kaebin Andres Ancheta, Emerson Mamaril Enipin, John Carlo Cruz Molina
  • MCM Package Isolation Through Leadframe Design and Package Saw Process
    Publication number: 20210320014
    Abstract: A method of making a semiconductor device includes mounting at least two semiconductor dies to a die pad of a leadframe in spaced apart relation to each other, the leadframe having a plurality of preformed leads, electrically connecting each semiconductor die to at least one preformed lead of the leadframe, forming a molding structure including at least part of the semiconductor dies and the preformed leads of the leadframe, and forming a trench in the molding structure in a space between the at least two semiconductor dies, the trench separating the die pad into first and second die pad portions.
    Type: Application
    Filed: June 23, 2021
    Publication date: October 14, 2021
    Inventors: Bernard Kaebin Andres Ancheta, Emerson Mamaril Enipin, John Carlo Cruz Molina
  • MCM package isolation through leadframe design and package saw process
    Patent number: 11081366
    Abstract: A method of making a semiconductor device includes mounting at least two semiconductor dies to a die pad of a leadframe in spaced apart relation to each other, the leadframe having a plurality of preformed leads, electrically connecting each semiconductor die to at least one preformed lead of the leadframe, forming a molding structure including at least part of the semiconductor dies and the preformed leads of the leadframe, and forming a trench in the molding structure in a space between the at least two semiconductor dies, the trench separating the die pad into first and second die pad portions.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: August 3, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Bernard Kaebin Andres Ancheta, Emerson Mamaril Enipin, John Carlo Cruz Molina
  • MCM PACKAGE ISOLATION THROUGH LEADFRAME DESIGN AND PACKAGE SAW PROCESS
    Publication number: 20200185234
    Abstract: A method of making a semiconductor device includes mounting at least two semiconductor dies to a die pad of a leadframe in spaced apart relation to each other, the leadframe having a plurality of preformed leads, electrically connecting each semiconductor die to at least one preformed lead of the leadframe, forming a molding structure including at least part of the semiconductor dies and the preformed leads of the leadframe, and forming a trench in the molding structure in a space between the at least two semiconductor dies, the trench separating the die pad into first and second die pad portions.
    Type: Application
    Filed: December 5, 2018
    Publication date: June 11, 2020
    Inventors: Bernard Kaebin Andres Ancheta, Emerson Mamaril Enipin, John Carlo Cruz Molina
  • Process of making a stacked semiconductor package having a clip
    Patent number: 8883567
    Abstract: A method of making a stacked semiconductor package having at least a leadframe, a first die mounted above and soldered to the lead frame and a first clip mounted above and soldered to the first die. The method includes positioning the leadframe, first die and first clip in a vertically stacked relationship and nonsolderingly locking the first clip in laterally nondisplaceble relationship with the leadframe. A stacked semiconductor package and an intermediate product produced in making a stacked semiconductor package are also disclosed.
    Type: Grant
    Filed: March 27, 2012
    Date of Patent: November 11, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Michael Todd Wyant, Patricia Sabran Conde, Vikas Gupta, Rajiv Dunne, Emerson Mamaril Enipin
  • Stacked Semiconductor Package
    Publication number: 20130256852
    Abstract: A method of making a stacked semiconductor package having at least a leadframe, a first die mounted above and soldered to the lead frame and a first clip mounted above and soldered to the first die. The method includes positioning the leadframe, first die and first clip in a vertically stacked relationship and nonsolderingly locking the first clip in laterally nondisplaceble relationship with the leadframe. A stacked semiconductor package and an intermediate product produced in making a stacked semiconductor package are also disclosed.
    Type: Application
    Filed: March 27, 2012
    Publication date: October 3, 2013
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Michael Todd Wyant, Patricia Sabran Conde, Vikas Gupta, Rajiv Dunne, Emerson Mamaril Enipin