Abstract: A matrix multiplier is described for multiplying sampled data in analog format by a matrix of stored values also in analog format and of positive or negative sign. The analog input quantity in the form of an electrical charge is applied to individual circuit elements making up the matrix. Each circuit element contains a capacitive storage means for encoding a stored value. An output term proportional to the product of the applied charge and the capacitance is produced in each circuit element. The input quantities are applied to the circuit elements in parallel by rows, and the output quantities are derived in parallel by columns to achieve matrix multiplication. In one form, the multiplier is a matrix of one stage charged coupled devices, each using a partitioned electrode storage site with the partitioning varying from element to element. The invention leads to a simple and high speed design. The invention is applicable to the computation of the Discrete Fourier Transformation.