Abstract: A lipid membrane structure containing an anti-membrane-type matrix metalloproteinase monoclonal antibody such as an anti-MT1-MMP monoclonal antibody as a component of the lipid membrane structure. Said structure can be utilized as a drug delivery system for efficiently delivering a medicinally active ingredient and/or a gene to tumor cells, neoplastic vessel and the like in which a membrane-type matrix metalloproteinase (MT-MMP) is expressed.

Abstract: A dental adhesive containing an acidic group-containing radically polymerizable monomer, a non-acidic radically polymerizable monomer, a chemical polymerization initiator and a filler, as well as a 2,4-diphenyl-4-methyl-1-pentene. When the dental adhesive is used for adhering a crown restorative to the tooth, an excess of cement swelling from the surface of adhesion can be favorably removed, the curing time can be suitably adjusted without decreasing the strength of adhesion to the tooth, and a change in the color tone of the cured body can be effectively suppressed.

Abstract: A method of increasing ion source lifetime in an ion implantation system uses the introduction of an inert gas, such as argon or xenon, into the halide-containing source gas. Inert gas constituents have a cleansing effect in the plasma ambient by enhancing sputtering.

Abstract: A dental adhesive containing an acidic group-containing radically polymerizable monomer, a non-acidic radically polymerizable monomer, a chemical polymerization initiator and a filler, as well as a 2,4-diphenyl-4-methyl-1-pentene. When the dental adhesive is used for adhering a crown restorative to the tooth, an excess of cement swelling from the surface of adhesion can be favorably removed, the curing time can be suitably adjusted without decreasing the strength of adhesion to the tooth, and a change in the color tone of the cured body can be effectively suppressed.

Abstract: A semiconductor device is provided with semiconducting sidewall spacers used in the formation of source/drain regions. The semiconducting sidewall spacers also reduce the possibility of suicide shorting through shallow source/drain junctions. Embodiments include doping the semiconducting sidewall spacers so that they serve as a source of impurities for forming source/drain extensions during activation annealing.

Abstract: A semiconductor device is provided with semiconducting sidewall spacers used in the formation of source/drain regions. The semiconducting sidewall spacers also reduce the possibility of silicide shorting through shallow source/drain junctions. Embodiments include doping the semiconducting sidewall spacers so that they serve as a source of impurities for forming source/drain extensions during activation annealing.

Abstract: Semiconductor devices comprising a plurality of active device regions formed in a common semiconductor substrate, e.g., CMOS devices, are formed by utilizing shallow trench isolation (STI) technology enhanced by selectively implanting the bottom surface of the trench with dopant diffusion inhibiting ions prior to filling the trench with a dielectric material and formation of opposite conductivity type well regions on either side of the trench. The inventive methodology effectively reduces or substantially eliminates deleterious counterdoping of the subsequently formed well regions resulting from thermally-induced lateral inter-diffusion of p-type and/or n-type dopant impurities used for forming the well regions.

Abstract: Submicron-dimensioned, MOSFET devices are formed using multiple implants for forming an impurity concentration distribution profile exhibiting three impurity concentration peaks at a predetermined depths below the semiconductor surface substrate. The inventive method reduces “latch-up” and “punch-through” with controllable adjustment of the threshold voltage.

Abstract: Depletion of dopant from polysilicon gate layers with attendant dopant penetration of underlying gate oxide layers of silicon-based MOS and CMOS transistor devices are reduced or substantially eliminated by a process wherein a thin, high-quality silicon oxide gate insulator layer initially formed on a surface of a heavily-doped polysilicon substrate. The oxide layer is then subjected to impurity ion implantation selected to penetrate a desired depth into the underlying semiconductor substrate for formation of a structurally weakened cleavage plane thereat. The cleaved substrate is then bonded, via the silicon oxide gate insulator layer, to a second, lightly- to moderately-doped semiconductor substrate of similar conductivity type. The thus-produced composite is then subjected to further processing for patterning of the heavily-doped gate and gate insulator layers and to define active areas for formation of source/drain regions in the second, lightly-doped substrate.

Abstract: Silicon-based, submicron-dimensioned MOS and/or CMOS transistor devices having substantially reduced source/drain junction-to-semiconductor substrate capacitance are formed by implanting oxygen atoms and/or molecules just below source/drain implant regions. Implantation conditions are selected to provide a peak oxygen implant concentration at a depth just below the ultimate source/drain junction depth. Subsequent thermal processing at elevated temperature results in source/drain dopant diffusion/activation and formation of a silicon oxide barrier layer or stratum just below the ultimate source/drain junction depth, thereby substantially reducing junction-to-substrate capacitance of refractory metal silicide-contact devices.

Abstract: Submicron-dimensioned MOS and/or CMOS transistors are fabricated by a process employing removable sidewall spacers made of a material, such as UV-nitride, which is readily etched in its as-deposited, undensified state but difficult-to-etch in its thermally annealed, densified state. The as-deposited, undensified spacers are removed by etching with dilute aqueous HF after implantation of moderately or heavily-doped source/drain regions but prior to annealing of the implants for dopant diffusion/activation and lattice damage relaxation. Lightly- or moderately doped, shallow-depth source/drain extensions are implanted and annealed after spacer removal.

Abstract: A method of reducing implant dose loss is provided. The method includes performing multiple low dose implant steps with interspersed anneal steps, thereby avoiding amorphous-silicon formation. The anneal steps may be performed at high temperatures or at low temperatures.

Abstract: A semiconductor device having a retrograde channel profile is achieved by forming a retrograde impurity region in the surface portion of a semiconductor substrate, and subsequently forming a semiconductor layer on the retrograde impurity region at a predetermined thickness. The thickness of the semiconductor layer is controlled to localize the retrograde impurity region and its impurity concentration peak at a predetermined depth, thereby reducing the device's susceptibility to “reverse short channel effects.

Abstract: Submicron-dimensioned MOS and/or CMOS transistors are fabricated by a process employing removable sidewall spacers made of a material, such as UV-nitride, which has been treated subsequent to its deposition, e.g., by ion implantation, to augment its etch rate with a room temperature etchant, e.g., dilute aqueous HF. The treated spacers are removed with the dilute, aqueous HF after implantation of moderately or heavily-doped source/drain regions but prior to any post-implantation annealing processing, in order not to increase the etch resistance of the spacer material by thermally-induced densification.

Abstract: A semiconductor device exhibiting a super-steep retrograde channel profile to reduce susceptibility to “latch up” is achieved by forming a high impurity concentration layer on a semiconductor substrate and forming a diffusion cap layer near the surface of the high impurity concentration layer. Subsequently, a low impurity concentration layer is formed on the diffusion cap layer of the high impurity concentration layer. The diffusion cap layer formed between the high and low impurity concentration layers substantially prevents the impurities contained in the high impurity concentration layer from diffusing into the overlying low impurity concentration layer, thereby achieving a super-steep retrograde channel profile.

Abstract: Submicron-dimensioned, p-channel MOS transistors and CMOS devices a formed using nitrogen and boron co-implants for forming p-type well regions, each implant having a parabolically-shaped concentration distribution profile. During subsequent thermal annealling, boron-doped wells are formed, each having a retrograde-shaped concentration distribution profile exhibiting a peak boron concentration at a preselected depth below the semiconductor substrate surface. The inventive method reduces “short-channel” effects such as “punch-through” while maintaining high channel mobility.

Abstract: Short channel effects are curtailed thereby increasing integrated circuit speed by forming a channel dopant with an asymmetric impurity concentration profile. Embodiments include ion implanting Si or Ge at a large tilt angle to amorphize a portion of a designated channel region with a varying degree of amorphization decreasing from the intended drain region to the intended source region, substantially vertically ion implanting channel dopant impurities and annealing. During annealing, diffusion is retarded in areas of increased amorphization, thereby forming an asymmetric impurity concentration gradient across the channel region increasing in the direction of the source region.

Abstract: An ultra-large-scale integrated (ULSI) circuit includes MOSFETs on an SOI substrate. The MOSFETs include elevated source and drain regions. The elevated source and drain regions are amorphized before doping. Neutral ion species can be utilized to amorphize the elevated source and drain region. Dopants are activated in a low-temperature rapid thermal anneal process.

Abstract: A MOS semiconductor device is formed with reduced parasitic junction capacitance and reduced gate resistance. Embodiments include forming oxide sidewall spacers on side surfaces of openings in a nitride layer exposing the substrate, and performing a channel implant. A thin gate oxide layer is then thermally grown on the exposed portion of the substrate, and a relatively thin polysilicon layer is deposited on the gate oxide layer and the spacers. A metal layer, such as tungsten, is then deposited filling the opening, and planarized, as by chemical-mechanical polishing, using the nitride layer as a polish stop. Source/drain regions are thereafter formed by ion implantation, and the source/drain regions are silicided.

Abstract: Submicron-dimensioned, silicon-based MOS-type transistor devices having reduced tendency for “latch up” are formed by removing residual indium dopant utilized for forming a retrograde-shaped indium doping concentration profile of the channel region from the surface and uppermost stratum of the silicon substrate by a rapid thermal annealing process prior to silicon oxide thin gate insulator formation. The inventive methodology substantially eliminates deleterious indium contamination of the gate insulator layer.