Patents by Inventor Emi Kanazaki
Emi Kanazaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7851867Abstract: An integrated circuit includes: a semiconductor substrate that has a well region containing a first conductivity type impurity; and an enhancement type MOS transistor and a plurality of depletion type MOS transistors, each of which is formed in the well region and has a channel region under a gate electrode. At least one of the depletion type MOS transistors has, in the channel region, an implantation region into which a second conductivity type impurity is implanted so that a threshold voltage is adjusted. The implantation region has the first conductivity type impurity and the second conductivity type impurity. Further, the second conductivity type impurity has a concentration that is higher than a concentration of the first conductivity type impurity.Type: GrantFiled: November 21, 2006Date of Patent: December 14, 2010Assignee: Panasonic CorporationInventors: Chinatsu Seto, Mikiya Uchida, Kenichi Mimuro, Emi Kanazaki
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Patent number: 7319061Abstract: In a method for fabricating an electronic device including a transistor with a drain extension structure, a correspondence between a size of a gate electrode of the transistor and ion implantation conditions or heat treatment conditions for forming the drain extension structure is previously obtained. This correspondence satisfies that the transistor has a given threshold voltage. After formation of the gate electrode and measurement of the size of the gate electrode, ion implantation conditions or heat treatment conditions for forming the drain extension structure are set based on the previously-obtained correspondence and the measured size of the gate electrode. Ion implantation or heat treatment for forming the drain extension structure is performed under the ion implantation conditions or heat treatment conditions that have been set.Type: GrantFiled: October 26, 2006Date of Patent: January 15, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Satoshi Shibata, Fumitoshi Kawase, Hisako Kamiyanagi, Emi Kanazaki
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Patent number: 7282416Abstract: In a method for fabricating an electronic device including a transistor with a drain extension structure, a correspondence between a size of a gate electrode of the transistor and ion implantation conditions or heat treatment conditions for forming the drain extension structure is previously obtained. This correspondence satisfies that the transistor has a given threshold voltage. After formation of the gate electrode and measurement of the size of the gate electrode, ion implantation conditions or heat treatment conditions for forming the drain extension structure are set based on the previously-obtained correspondence and the measured size of the gate electrode. Ion implantation or heat treatment for forming the drain extension structure is performed under the ion implantation conditions or heat treatment conditions that have been set.Type: GrantFiled: October 4, 2005Date of Patent: October 16, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Satoshi Shibata, Fumitoshi Kawase, Hisako Kamiyanagi, Emi Kanazaki
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Publication number: 20070228495Abstract: An integrated circuit includes: a semiconductor substrate that has a well region containing a first conductivity type impurity; and an enhancement type MOS transistor and a plurality of depletion type MOS transistors, each of which is formed in the well region and has a channel region under a gate electrode. At least one of the depletion type MOS transistors has, in the channel region, an implantation region into which a second conductivity type impurity is implanted so that a threshold voltage is adjusted. The implantation region has the first conductivity type impurity and the second conductivity type impurity. Further, the second conductivity type impurity has a concentration that is higher than a concentration of the first conductivity type impurity.Type: ApplicationFiled: November 21, 2006Publication date: October 4, 2007Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Chinatsu SETO, Mikiya UCHIDA, Ken MIMURO, Emi KANAZAKI
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Publication number: 20070048918Abstract: In a method for fabricating an electronic device including a transistor with a drain extension structure, a correspondence between a size of a gate electrode of the transistor and ion implantation conditions or heat treatment conditions for forming the drain extension structure is previously obtained. This correspondence satisfies that the transistor has a given threshold voltage. After formation of the gate electrode and measurement of the size of the gate electrode, ion implantation conditions or heat treatment conditions for forming the drain extension structure are set based on the previously-obtained correspondence and the measured size of the gate electrode. Ion implantation or heat treatment for forming the drain extension structure is performed under the ion implantation conditions or heat treatment conditions that have been set.Type: ApplicationFiled: October 26, 2006Publication date: March 1, 2007Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Satoshi Shibata, Fumitoshi Kawase, Hisako Kamiyanagi, Emi Kanazaki
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Patent number: 7103271Abstract: A light irradiation heat treatment apparatus and method may use a plane-shaped light irradiation heating component, facing one surface of a workpiece supported in a furnace, to raise the temperature of the workpiece. The temperature of the workpiece is raised by setting an intensity distribution for light irradiated from the light irradiation heating component in accordance with the resistivity of the workpiece. Thereafter, the workpiece is irradiated with light having the set light intensity distribution to raise its temperature.Type: GrantFiled: December 1, 2004Date of Patent: September 5, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Emi Kanazaki, Satoshi Shibata, Fumitoshi Kawase
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Publication number: 20060079044Abstract: In a method for fabricating an electronic device including a transistor with a drain extension structure, a correspondence between a size of a gate electrode of the transistor and ion implantation conditions or heat treatment conditions for forming the drain extension structure is previously obtained. This correspondence satisfies that the transistor has a given threshold voltage. After formation of the gate electrode and measurement of the size of the gate electrode, ion implantation conditions or heat treatment conditions for forming the drain extension structure are set based on the previously-obtained correspondence and the measured size of the gate electrode. Ion implantation or heat treatment for forming the drain extension structure is performed under the ion implantation conditions or heat treatment conditions that have been set.Type: ApplicationFiled: October 4, 2005Publication date: April 13, 2006Inventors: Satoshi Shibata, Fumitoshi Kawase, Hisako Kamiyanagi, Emi Kanazaki
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Publication number: 20050173386Abstract: A distribution is given to a light irradiation intensity at a temperature rise process after starting a light irradiation (open loop control process), and temperature variation of the workpiece is reduced, so that thermal stress applied to a workpiece is reduced. A light irradiation heat treatment method for supporting a workpiece in a furnace, and heat-treating the workpiece by means of plane-shaped light irradiation heating means provided so as to face to one surface of the workpiece includes a process for irradiating a light having a flat intensity distribution to the workpiece from the light irradiation heating means and raising the temperature of the workpiece. In the open loop control process after starting the light irradiation, the temperature variation of the workpiece can be reduced by setting the light irradiation intensity for every plurality of areas.Type: ApplicationFiled: December 1, 2004Publication date: August 11, 2005Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Emi Kanazaki, Satoshi Shibata, Fumitoshi Kawase