Patents by Inventor Emi KASHIWAYA

Emi KASHIWAYA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Wiring board and method of manufacturing a semiconductor device
    Patent number: 8878070
    Abstract: A wiring board of this invention includes a product formation area in which are arranged a plurality of product formation sections on which a semiconductor chip is mounted; a molding area that is provided on an outer circumferential side of the product formation area, and with which a seal portion that covers the semiconductor chips mounted on the product formation sections makes contact; a clamp area that is provided on an outer circumferential side of the molding area, and that is held by a molding die that forms the seal portion; wiring that is provided in the product formation area, and that is electrically connected to the semiconductor chips; a first solid pattern that is provided in the molding area, and in which a plurality of dots are arranged; and a second solid pattern that is provided in the clamp area, and in which a plurality of dots that are larger than the dots of the first solid pattern are arranged.
    Type: Grant
    Filed: August 31, 2011
    Date of Patent: November 4, 2014
    Assignee: PS4 Luxco S.A.R.L.
    Inventors: Emi Kashiwaya, Osamu Kindo, Noriou Shimada
  • WIRING BOARD AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
    Publication number: 20120048595
    Abstract: A wiring board of this invention includes a product formation area in which are arranged a plurality of product formation sections on which a semiconductor chip is mounted; a molding area that is provided on an outer circumferential side of the product formation area, and with which a seal portion that covers the semiconductor chips mounted on the product formation sections makes contact; a clamp area that is provided on an outer circumferential side of the molding area, and that is held by a molding die that forms the seal portion; wiring that is provided in the product formation area, and that is electrically connected to the semiconductor chips; a first solid pattern that is provided in the molding area, and in which a plurality of dots are arranged; and a second solid pattern that is provided in the clamp area, and in which a plurality of dots that are larger than the dots of the first solid pattern are arranged.
    Type: Application
    Filed: August 31, 2011
    Publication date: March 1, 2012
    Inventors: Emi KASHIWAYA, Osamu KINDO, Noriou SHIMADA