Abstract: A hybrid multicarrier RF power amplifier linearization architecture combines ACT and feed-forward amplifier stages to achieve high output distortion rejection and enhanced amplifier linearity. A carrier cancellation loop is coupled with a main RF power amplifier stage having parallel RF power amplifiers coupled via intermod-complementing predistortion paths. The carrier cancellation loop is coupled to a feed-forward loop containing a feed-forward RF power amplifier, to produce a composite amplified output signal having very reduced intermodulation products. Vector modulators in the main amplifier and feed-forward amplifier stages are controlled by a digital signal processor, using outputs from various monitoring subsystems, including pilot tone detection, correlator, distortion and power detector circuits.

Abstract: A dual-mode successive detection amplifier for providing a first output signal corresponding to a logarithmic function of a RF input signal, and for providing a second limited RF output signal is disclosed herein. A RF input signal is applied to the first of a succession of amplification stages arranged along a RF signal path to cascade amplify the RF input signal into the limited RF output signal. A plurality of detector/limiter (D/L) circuits interposed between the amplification stages limit RF signal energy propagating along the RF signal path so as to prevent saturation of the amplification stages. The D/L modules also provide a succession of detection signals corresponding to video envelopes of the RF signal energy produced by each of the amplification stages. The detection signals are applied to a video summation line and therein summed to produce the logarithmic output signal.

Abstract: An RF amplifier including first and second FETs which are interconnected to function as a single transistor with improved gate. An input signal is applied across the gate and source of the first FET, and an output signal is obtained across the drain and source of the second transistor. RF coupling of the FETs is provided by first and second serially connected transmission lines connected between the drain of the first FET and the gate of the second FET. A third transmission line connects the common terminal of the first and second transmission line to circuit ground. In a preferred embodiment, the amplifier comprises a monolithic circuit formed in gallium arsenide with the transmission lines comprising microstrip.